{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,9]],"date-time":"2026-07-09T16:16:10Z","timestamp":1783613770617,"version":"3.55.0"},"publisher-location":"New York, NY, USA","reference-count":25,"publisher":"ACM","license":[{"start":{"date-parts":[[2014,3,30]],"date-time":"2014-03-30T00:00:00Z","timestamp":1396137600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2014,3,30]]},"DOI":"10.1145\/2560519.2560524","type":"proceedings-article","created":{"date-parts":[[2014,4,1]],"date-time":"2014-04-01T13:07:05Z","timestamp":1396357625000},"page":"69-76","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":18,"title":["Clock tree resynthesis for multi-corner multi-mode timing closure"],"prefix":"10.1145","author":[{"given":"Subhendu","family":"Roy","sequence":"first","affiliation":[{"name":"University of Texas at Austin, Austin, TX, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Pavlos M.","family":"Mattheakis","sequence":"additional","affiliation":[{"name":"Mentor Graphics Inc., Grenoble, France"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Laurent","family":"Masse-Navette","sequence":"additional","affiliation":[{"name":"Mentor Graphics Inc., Grenoble, France"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"David Z.","family":"Pan","sequence":"additional","affiliation":[{"name":"University of Texas at Austin, Austin, TX, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2014,3,30]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.205004"},{"key":"e_1_3_2_1_2_1","first-page":"17","volume-title":"Zero skew clock-routing trees with minimum wirelength,\" ASIC Conference and Exhibit","author":"Boese K. D.","year":"1992","unstructured":"K. D. Boese and A. B. Kahng , \" Zero skew clock-routing trees with minimum wirelength,\" ASIC Conference and Exhibit , pp. 17 -- 21 , 1992 . K. D. Boese and A. B. Kahng, \"Zero skew clock-routing trees with minimum wirelength,\" ASIC Conference and Exhibit, pp. 17--21, 1992."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.825875"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.55696"},{"key":"e_1_3_2_1_5_1","first-page":"407","volume-title":"A graph-theoretic approach to clock skew optimization,\" ISCAS","author":"Deokar R.","year":"1994","unstructured":"R. Deokar and S. Sapatnekar , \" A graph-theoretic approach to clock skew optimization,\" ISCAS , pp. 407 -- 410 , 1994 . R. Deokar and S. Sapatnekar, \"A graph-theoretic approach to clock skew optimization,\" ISCAS, pp. 407--10, 1994."},{"key":"e_1_3_2_1_6_1","first-page":"283","volume-title":"Retiming and clock skew for synchronous systems,\" ISCAS","author":"Chao L. F.","year":"1994","unstructured":"L. F. Chao and H. M. Sha , \" Retiming and clock skew for synchronous systems,\" ISCAS , pp. 283 -- 286 , 1994 . L. F. Chao and H. M. Sha, \"Retiming and clock skew for synchronous systems,\" ISCAS, pp. 283--86, 1994."},{"key":"e_1_3_2_1_7_1","first-page":"239","volume-title":"Clock skew scheduling for improved reliability via quadratic programming,\" ICCAD","author":"Kourtev I. S.","year":"1999","unstructured":"I. S. Kourtev and E. G. Friedman , \" Clock skew scheduling for improved reliability via quadratic programming,\" ICCAD , pp. 239 -- 243 , 1999 . I. S. Kourtev and E. G. Friedman, \"Clock skew scheduling for improved reliability via quadratic programming,\" ICCAD, pp. 239--43, 1999."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/309847.309919"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233508"},{"key":"e_1_3_2_1_10_1","first-page":"486","volume-title":"CMOS scaling in nanometer regime,\" Proc","author":"Taur Y.","year":"1997","unstructured":"Y. Taur and D. Buchanan , \" CMOS scaling in nanometer regime,\" Proc . IEEE , pp. 486 -- 503 , 1997 . Y. Taur and D. Buchanan, \"CMOS scaling in nanometer regime,\" Proc. IEEE, pp. 486--503, 1997."},{"key":"e_1_3_2_1_11_1","first-page":"4","volume-title":"Conference","author":"Mehrotra V.","year":"2001","unstructured":"V. Mehrotra and D. Boning , \" Technology scaling impact of variation on clock skew and interconnecet delay,\" Interconnect Tech . Conference , pp. 4 -- 6 , 2001 . V. Mehrotra and D. Boning, \"Technology scaling impact of variation on clock skew and interconnecet delay,\" Interconnect Tech. Conference, pp. 4--6, 2001."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391654"},{"key":"e_1_3_2_1_13_1","unstructured":"S. Jilla \"Multi-corner multi-mode signal integrity optimization \" EDA Tech Forum 2008.  S. Jilla \"Multi-corner multi-mode signal integrity optimization \" EDA Tech Forum 2008."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1960397.1960425"},{"key":"e_1_3_2_1_15_1","first-page":"2040","volume-title":"Clock-tree aware placement based on dynamic clock-tree building,\" ISCAS","author":"Wang Y.","year":"2007","unstructured":"Y. Wang , Q. Zhou , X. Hong , and Y. Cai , \" Clock-tree aware placement based on dynamic clock-tree building,\" ISCAS , pp. 2040 -- 2043 , 2007 . Y. Wang, Q. Zhou, X. Hong, and Y. Cai, \"Clock-tree aware placement based on dynamic clock-tree building,\" ISCAS, pp. 2040--43, 2007."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/640000.640016"},{"key":"e_1_3_2_1_17_1","first-page":"101","volume-title":"Delay-optimal simultaneous technology mapping and placement with applications to timing optimization,\" ICCAD","author":"Liu Y.","year":"2008","unstructured":"Y. Liu , R. S. Shelar , and J. Hu , \" Delay-optimal simultaneous technology mapping and placement with applications to timing optimization,\" ICCAD , pp. 101 -- 106 , 2008 . Y. Liu, R. S. Shelar, and J. Hu, \"Delay-optimal simultaneous technology mapping and placement with applications to timing optimization,\" ICCAD, pp. 101--106, 2008."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.828552"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/240518.240659"},{"key":"e_1_3_2_1_20_1","first-page":"530","volume-title":"ECO timing optimization using spare cells,\" ICCAD","author":"Chen Y. P.","year":"2007","unstructured":"Y. P. Chen , J. W. Fang , and Y. W. Chang , \" ECO timing optimization using spare cells,\" ICCAD , pp. 530 -- 535 , 2007 . Y. P. Chen, J. W. Fang, and Y. W. Chang, \"ECO timing optimization using spare cells,\" ICCAD, pp. 530--535, 2007."},{"key":"e_1_3_2_1_21_1","first-page":"755","volume-title":"A revisit to the primal-dual based clock skew scheduling algorithm,\" ISQED","author":"Ni M.","year":"2010","unstructured":"M. Ni and S. O. Memik , \" A revisit to the primal-dual based clock skew scheduling algorithm,\" ISQED , pp. 755 -- 764 , 2010 . M. Ni and S. O. Memik, \"A revisit to the primal-dual based clock skew scheduling algorithm,\" ISQED, pp. 755--764, 2010."},{"key":"e_1_3_2_1_23_1","first-page":"224","volume-title":"Post-CTS clock skew scheduling with limited delay buffering,\" International Midwest Symposium on Circuits and Systems","author":"Lu J.","year":"2009","unstructured":"J. Lu and B. Taskin , \" Post-CTS clock skew scheduling with limited delay buffering,\" International Midwest Symposium on Circuits and Systems , pp. 224 -- 227 , 2009 . J. Lu and B. Taskin, \"Post-CTS clock skew scheduling with limited delay buffering,\" International Midwest Symposium on Circuits and Systems, pp. 224--227, 2009."},{"key":"e_1_3_2_1_24_1","first-page":"62","volume-title":"Useful clock skew optimization under a multi-corner multi-mode design framework,\" ISQED","author":"Shen W.","year":"2010","unstructured":"W. Shen , Y. Cai , W. Chen , Y. Lu , Q. Zhou , and J. Hu , \" Useful clock skew optimization under a multi-corner multi-mode design framework,\" ISQED , pp. 62 -- 68 , 2010 . W. Shen, Y. Cai, W. Chen, Y. Lu, Q. Zhou, and J. Hu, \"Useful clock skew optimization under a multi-corner multi-mode design framework,\" ISQED, pp. 62--68, 2010."},{"key":"e_1_3_2_1_25_1","unstructured":"V. Ramachandran \"Functional skew aware clock tree synthesis \" ISPD 2012.  V. Ramachandran \"Functional skew aware clock tree synthesis \" ISPD 2012."},{"key":"e_1_3_2_1_26_1","volume-title":"Static Timing Analysis for Nanometer Designs: A Practical Approach","author":"Bhaskar J.","year":"2009","unstructured":"J. Bhaskar and R. Chadha , Static Timing Analysis for Nanometer Designs: A Practical Approach . Springer , 2009 . J. Bhaskar and R. Chadha, Static Timing Analysis for Nanometer Designs: A Practical Approach. Springer, 2009."}],"event":{"name":"ISPD'14: International Symposium on Physical Design","location":"Petaluma California USA","acronym":"ISPD'14","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 2014 on International symposium on physical design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2560519.2560524","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2560519.2560524","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:10:21Z","timestamp":1750234221000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2560519.2560524"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,3,30]]},"references-count":25,"alternative-id":["10.1145\/2560519.2560524","10.1145\/2560519"],"URL":"https:\/\/doi.org\/10.1145\/2560519.2560524","relation":{},"subject":[],"published":{"date-parts":[[2014,3,30]]},"assertion":[{"value":"2014-03-30","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}