{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:52:09Z","timestamp":1750308729121,"version":"3.41.0"},"reference-count":37,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2014,2,1]],"date-time":"2014-02-01T00:00:00Z","timestamp":1391212800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100002855","name":"Ministry of Science and Technology of the People's Republic of China","doi-asserted-by":"publisher","award":["2009AA01Z129"],"award-info":[{"award-number":["2009AA01Z129"]}],"id":[{"id":"10.13039\/501100002855","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["60425203, 60910003, 61373021, and 61170063"],"award-info":[{"award-number":["60425203, 60910003, 61373021, and 61170063"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2014,2]]},"abstract":"<jats:p>The three-dimensional (3-D) technology offers a new solution to the increasing density of integrated circuits (ICs). In this work, we propose novel scan architectures for 3-D IC pre-bond and post-bond testing by considering the interconnection overhead of through-silicon-vias (TSVs). Since hotspots in 3-D ICs often cause performance and reliability issues, we also develop different test ordering schemes for prebond and postbond testing to avoid applying test vectors that could worsen the temperature distribution. Experimental results show that the peak temperature can be lowered by 20% with the 3-D scan tree architecture. When combined with the test ordering scheme, the 3-D scan tree can further reduce peak temperature by over 30%.<\/jats:p>","DOI":"10.1145\/2564922","type":"journal-article","created":{"date-parts":[[2014,3,4]],"date-time":"2014-03-04T13:24:59Z","timestamp":1393939499000},"page":"1-19","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["A thermal-driven test application scheme for pre-bond and post-bond scan testing of three-dimensional ICs"],"prefix":"10.1145","volume":"10","author":[{"given":"Dong","family":"Xiang","sequence":"first","affiliation":[{"name":"Tsinghua University, Beijing, China"}]},{"given":"Kele","family":"Shen","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China"}]}],"member":"320","published-online":{"date-parts":[[2014,3,6]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.895840"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2009.42"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2048359"},{"volume-title":"Proceedings of the International Conference on Computer-Aided Design. 149--154","author":"Chen Z.","key":"e_1_2_1_4_1","unstructured":"Z. Chen , K. Chakrabarty , and D. Xiang . 2010. MVP: Capture-power reduction with minimum-violations partitioning for delay testing . In Proceedings of the International Conference on Computer-Aided Design. 149--154 . Z. Chen, K. Chakrabarty, and D. Xiang. 2010. MVP: Capture-power reduction with minimum-violations partitioning for delay testing. In Proceedings of the International Conference on Computer-Aided Design. 149--154."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2009.15"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.119"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.870069"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-007-5030-6"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.876103"},{"volume-title":"Proceedings of the Design Automation, and Test in Europe. 220--225","author":"Jiang L.","key":"e_1_2_1_10_1","unstructured":"L. Jiang , L. Huang , and Q. Xu . 2009a. Test architecture design and optimization for three-dimensional SoCs . In Proceedings of the Design Automation, and Test in Europe. 220--225 . L. Jiang, L. Huang, and Q. Xu. 2009a. Test architecture design and optimization for three-dimensional SoCs. In Proceedings of the Design Automation, and Test in Europe. 220--225."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687434"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.748202"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.125"},{"key":"e_1_2_1_14_1","volume-title":"Proceedings of the Annual Symposium on VLSI. 139--144","author":"Lewis D. L.","year":"2009","unstructured":"D. L. Lewis and H. H. S. Lee . 2009 . High-frequency, at-speed scan testing . In Proceedings of the Annual Symposium on VLSI. 139--144 . D. L. Lewis and H. H. S. Lee. 2009. High-frequency, at-speed scan testing. In Proceedings of the Annual Symposium on VLSI. 139--144."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2042896"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2208644"},{"volume-title":"Proceedings of the International Conference on Computer Design. 474--479","author":"Li J.","key":"e_1_2_1_17_1","unstructured":"J. Li and D. Xiang . 2010. DFT optimization for pre-bond testing of 3D-SICs containing TSVs . In Proceedings of the International Conference on Computer Design. 474--479 . J. Li and D. Xiang. 2010. DFT optimization for pre-bond testing of 3D-SICs containing TSVs. In Proceedings of the International Conference on Computer Design. 474--479."},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2005.66"},{"volume-title":"Proceedings of the International Test Conference. 1--11","author":"Marinissen E. J.","key":"e_1_2_1_19_1","unstructured":"E. J. Marinissen and Y. Zorian . 2009. Testing 3-D chips containing through-silicon vias . In Proceedings of the International Test Conference. 1--11 . E. J. Marinissen and Y. Zorian. 2009. Testing 3-D chips containing through-silicon vias. In Proceedings of the International Test Conference. 1--11."},{"volume-title":"Proceedings of the 3-D Systems Integration Conference.","author":"Marinissen E. J.","key":"e_1_2_1_20_1","unstructured":"E. J. Marinissen , C. C. Chi , J. Verbree , and M. Konijnenburg . 2010. 3-D DfT architecture for pre-bond and post-bond testing . In Proceedings of the 3-D Systems Integration Conference. E. J. Marinissen, C. C. Chi, J. Verbree, and M. Konijnenburg. 2010. 3-D DfT architecture for pre-bond and post-bond testing. In Proceedings of the 3-D Systems Integration Conference."},{"volume-title":"Proceedings of the International Test Conference.","author":"Noia B.","key":"e_1_2_1_21_1","unstructured":"B. Noia , K. Chakrabarty , and E. J. Marinissen . 2010. Optimization methods for post-bond die-internal\/external testing in 3-D stacked ICs . In Proceedings of the International Test Conference. B. Noia, K. Chakrabarty, and E. J. Marinissen. 2010. Optimization methods for post-bond die-internal\/external testing in 3-D stacked ICs. In Proceedings of the International Test Conference."},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2160177"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/1127908.1127915"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2008926"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/774572.774617"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2030353"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2015741"},{"key":"e_1_2_1_28_1","volume-title":"Proceedings of the IEEE Asian Test Symposium. 263--268","author":"Wu C.-W.","year":"2010","unstructured":"C.-W. Wu , P.-Y. Chen , and D.-M. Kwai . 2010 . On-chip testing of blind-via and open sleeve TSVs for 3D ICs before bonding . In Proceedings of the IEEE Asian Test Symposium. 263--268 . C.-W. Wu, P.-Y. Chen, and D.-M. Kwai. 2010. On-chip testing of blind-via and open sleeve TSVs for 3D ICs before bonding. In Proceedings of the IEEE Asian Test Symposium. 263--268."},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/1543438.1543442"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.1002"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2011.74"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2066070"},{"key":"e_1_2_1_33_1","doi-asserted-by":"crossref","unstructured":"Y. Xie J. Cong and S. Sapatnekar. 2009. Three-Dimensional Integrated Circuit Design: EDA Design and Microarchitecture. Springer.   Y. Xie J. Cong and S. Sapatnekar. 2009. Three-Dimensional Integrated Circuit Design: EDA Design and Microarchitecture. Springer.","DOI":"10.1007\/978-1-4419-0784-4"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/1148015.1148016"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882589"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2098130"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2009.27"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2564922","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2564922","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T20:14:53Z","timestamp":1750277693000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2564922"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,2]]},"references-count":37,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2014,2]]}},"alternative-id":["10.1145\/2564922"],"URL":"https:\/\/doi.org\/10.1145\/2564922","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"type":"print","value":"1550-4832"},{"type":"electronic","value":"1550-4840"}],"subject":[],"published":{"date-parts":[[2014,2]]},"assertion":[{"value":"2012-02-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2013-01-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2014-03-06","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}