{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,13]],"date-time":"2025-09-13T16:33:52Z","timestamp":1757781232745,"version":"3.41.0"},"reference-count":34,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2014,2,1]],"date-time":"2014-02-01T00:00:00Z","timestamp":1391212800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100004351","name":"Cisco Systems","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100004351","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","award":["2094"],"award-info":[{"award-number":["2094"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2014,2]]},"abstract":"<jats:p>\n            Circuit reliability analysis at the presilicon stage has become vital for sub-45nm technology designs in particular, due to aging effects, such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI). To avoid potential reliability hazards in the postsilicon stage, current large-scale designs for commercial implementation overpessimistically analyze circuit aging under assumed worst-case workload in order not to violate the corner cases even for low possibilities, thus introducing unnecessary margin in the design timing analysis. The major issue is lack of an effective aging analysis method applicable to large designs with low CPU runtime, which is mainly due to: (1) conventional reliability tools are extremely time-consuming for circuit-level timing analysis and thus are not practical for large designs; (2) mathematical models developed to expedite the process are not accurate due to the high complexity of aging effects. In this article, a comprehensive analysis is presented to highlight the importance of each aging parameter. Then, a novel methodology is developed based on current commercial reliability tools to guarantee its high accuracy on circuit-level aging analysis. Existing proven low-level mathematical models are further enhanced to extensively speed up a higher level analysis by taking advantage of the explicit intermediate conditions stored in a pregenerated lookup table. Our results indicate \u2265244\n            <jats:italic>X<\/jats:italic>\n            improved computational efficiency, \u22645% relative error, and \u22640.7% absolute error compared with commercial reliability analysis tools (e.g., HSPICE MOSRA).\n          <\/jats:p>","DOI":"10.1145\/2564926","type":"journal-article","created":{"date-parts":[[2014,3,4]],"date-time":"2014-03-04T13:24:59Z","timestamp":1393939499000},"page":"1-21","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":10,"title":["Critical-reliability path identification and delay analysis"],"prefix":"10.1145","volume":"10","author":[{"given":"Jifeng","family":"Chen","sequence":"first","affiliation":[{"name":"University of Connecticut, Storrs CT"}]},{"given":"Shuo","family":"Wang","sequence":"additional","affiliation":[{"name":"University of Connecticut, Storrs CT"}]},{"given":"Mohammad","family":"Tehranipoor","sequence":"additional","affiliation":[{"name":"University of Connecticut, Storrs CT"}]}],"member":"320","published-online":{"date-parts":[[2014,3,6]]},"reference":[{"issue":"4","key":"e_1_2_1_1_1","first-page":"1","article-title":"A critical examination of the mechanics of dynamic NBTI for PMOSFETS","volume":"14","author":"Alam M.","year":"2003","unstructured":"M. Alam . 2003 . A critical examination of the mechanics of dynamic NBTI for PMOSFETS . In Proceedings of the IEEE International Electron Devices Meeting (IEDM). 14 . 4 . 1 -- 14 .4.4. M. Alam. 2003. A critical examination of the mechanics of dynamic NBTI for PMOSFETS. In Proceedings of the IEEE International Electron Devices Meeting (IEDM). 14.4.1--14.4.4.","journal-title":"Proceedings of the IEEE International Electron Devices Meeting (IEDM)."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2008.107"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.110"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147115"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2002.805750"},{"volume-title":"Proceedings of the IEEE North Atlantic Test Workshop (NATW).","author":"Chen J.","key":"e_1_2_1_6_1","unstructured":"J. Chen , S. Wang , N. Bidokhti , and M. Tehranipoor . 2011. A framework for fast and accurate critical-reliability paths identification . In Proceedings of the IEEE North Atlantic Test Workshop (NATW). J. Chen, S. Wang, N. Bidokhti, and M. Tehranipoor. 2011. A framework for fast and accurate critical-reliability paths identification. In Proceedings of the IEEE North Atlantic Test Workshop (NATW)."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2008.919322"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10766-009-0104-y"},{"volume-title":"Proceedings of the 45th Annual IEEE International Reliability Physics Symposium. 268--280","author":"Grasser T.","key":"e_1_2_1_9_1","unstructured":"T. Grasser , W. Gos , V. Sverdlov , and B. Kaczer . 2007. The universality of NBTI relaxation and its implications for modeling and characterization . In Proceedings of the 45th Annual IEEE International Reliability Physics Symposium. 268--280 . T. Grasser, W. Gos, V. Sverdlov, and B. Kaczer. 2007. The universality of NBTI relaxation and its implications for modeling and characterization. In Proceedings of the 45th Annual IEEE International Reliability Physics Symposium. 268--280."},{"key":"e_1_2_1_10_1","doi-asserted-by":"crossref","unstructured":"K. Kang S. Gangwal S. Park and K. Roy. 2008. NBTI induced performance degradation in logic and memory circuits: How effectively can we approach a reliability solution&quest; In Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC). 726--731.   K. Kang S. Gangwal S. Park and K. Roy. 2008. NBTI induced performance degradation in logic and memory circuits: How effectively can we approach a reliability solution&quest; In Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC). 726--731.","DOI":"10.1109\/ASPDAC.2008.4484047"},{"volume-title":"Proceedings of International Conference on Computer Design (ICCD). 216--221","author":"Kang K.","key":"e_1_2_1_11_1","unstructured":"K. Kang , H. Kufluoglu , M. Alain , and K. Roy . 2006. Efficient transistor-level sizing technique under temporal performance degradation due to NBTI . In Proceedings of International Conference on Computer Design (ICCD). 216--221 . K. Kang, H. Kufluoglu, M. Alain, and K. Roy. 2006. Efficient transistor-level sizing technique under temporal performance degradation due to NBTI. In Proceedings of International Conference on Computer Design (ICCD). 216--221."},{"volume-title":"Proceedings of the Symposium on VLSI Technology. 73--74","author":"Kimizuka N.","key":"e_1_2_1_12_1","unstructured":"N. Kimizuka , T. Yamamoto , T. Mogami , K. Yamaguchi , K. Imai , and T. Horiuchi . 1999. The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling . In Proceedings of the Symposium on VLSI Technology. 73--74 . N. Kimizuka, T. Yamamoto, T.Mogami, K. Yamaguchi, K. Imai, and T. Horiuchi. 1999. The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling. In Proceedings of the Symposium on VLSI Technology. 73--74."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278574"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233601"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.506133"},{"volume-title":"Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS). 3--8.","author":"Lorenz D.","key":"e_1_2_1_16_1","unstructured":"D. Lorenz , G. Georgakos , and U. Schlichtmann . 2009. Aging analysis of circuit timing considering NBTI and HCI . In Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS). 3--8. D. Lorenz, G. Georgakos, and U. Schlichtmann. 2009. Aging analysis of circuit timing considering NBTI and HCI. In Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS). 3--8."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630044"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2009.5280815"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevB.51.4218"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2005.852523"},{"volume-title":"Proceedings of Design, Automation and Test in Europe (DATE). 1--6.","author":"Paul B.","key":"e_1_2_1_21_1","unstructured":"B. Paul , K. Kang , H. Kufluoglu , M. Ashrafulalam , and K. Roy . 2006. Temporal performance degradation under NBTI: Estimation and design for improved reliability of nanoscale circuits . In Proceedings of Design, Automation and Test in Europe (DATE). 1--6. B. Paul, K. Kang, H. Kufluoglu, M. Ashrafulalam, and K. Roy. 2006. Temporal performance degradation under NBTI: Estimation and design for improved reliability of nanoscale circuits. In Proceedings of Design, Automation and Test in Europe (DATE). 1--6."},{"volume-title":"Proceedings of JSSC. 548--594","author":"Sakurai T.","key":"e_1_2_1_22_1","unstructured":"T. Sakurai and A. R. Newton . 1990. Alpha-power law MOSFET model and its application to CMOS logic . In Proceedings of JSSC. 548--594 . T. Sakurai and A. R. Newton. 1990. Alpha-power law MOSFET model and its application to CMOS logic. In Proceedings of JSSC. 548--594."},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.1567461"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2009.4810381"},{"key":"e_1_2_1_25_1","unstructured":"E. Takeda C. Yang and A. Miura-Hamada. 1995. Hot-Carrier Effects In MOS Devices. Academic Press San Diego CA.  E. Takeda C. Yang and A. Miura-Hamada. 1995. Hot-Carrier Effects In MOS Devices. Academic Press San Diego CA."},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065793"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147172"},{"volume-title":"Proceedings of the IEEE Custom Integrated Circuits Conference (CICC). 13--16","author":"Wang W.","key":"e_1_2_1_28_1","unstructured":"W. Wang , V. Reddy , B. Yang , V. Balakrishnan , S. Krishnan , and Y. Cao . 2008a. Statistical prediction of circuit aging under process variations . In Proceedings of the IEEE Custom Integrated Circuits Conference (CICC). 13--16 . W. Wang, V. Reddy, B. Yang, V. Balakrishnan, S. Krishnan, and Y. Cao. 2008a. Statistical prediction of circuit aging under process variations. In Proceedings of the IEEE Custom Integrated Circuits Conference (CICC). 13--16."},{"volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD). 735--740","author":"Wang W.","key":"e_1_2_1_29_1","unstructured":"W. Wang , Z. Wei , S. Yang , and Y. Cao . 2007a. An efficient method to identify critical gates under circuit aging . In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD). 735--740 . W. Wang, Z. Wei, S. Yang, and Y. Cao. 2007a. An efficient method to identify critical gates under circuit aging. In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD). 735--740."},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278573"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2008810"},{"volume-title":"Proceedings of the 9th International Symposium on Quality Electronic Design (ISQED). 763--768","author":"Wang W.","key":"e_1_2_1_32_1","unstructured":"W. Wang , S. Yang , and Y. Cao . 2008b. Node criticality computation for circuit timing analysis and optimization under NBTI effect . In Proceedings of the 9th International Symposium on Quality Electronic Design (ISQED). 763--768 . W. Wang, S. Yang, and Y. Cao. 2008b. Node criticality computation for circuit timing analysis and optimization under NBTI effect. In Proceedings of the 9th International Symposium on Quality Electronic Design (ISQED). 763--768."},{"volume-title":"Proceedings of the IEEE First International Symposium on Quality Electronic Design (ISQED). 73--79","author":"Wu L.","key":"e_1_2_1_33_1","unstructured":"L. Wu , J. Fang , H. Yonezawa , Y. Kawakami , N. Iwanishi , H. Yan , P. Chen , A. I.-.H. Chen , N. Koike , Y. Okamoto , C.-S. Yeh , and Z. Liu . 2000. Glacier: A hot carrier gate level circuit characterization and simulation system for VLSI design . In Proceedings of the IEEE First International Symposium on Quality Electronic Design (ISQED). 73--79 . L. Wu, J. Fang, H. Yonezawa, Y. Kawakami, N. Iwanishi, H. Yan, P. Chen, A. I.-.H. Chen, N. Koike, Y. Okamoto, C.-S. Yeh, and Z. Liu. 2000. Glacier: A hot carrier gate level circuit characterization and simulation system for VLSI design. In Proceedings of the IEEE First International Symposium on Quality Electronic Design (ISQED). 73--79."},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2002.1015228"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2564926","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2564926","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T20:22:00Z","timestamp":1750278120000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2564926"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,2]]},"references-count":34,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2014,2]]}},"alternative-id":["10.1145\/2564926"],"URL":"https:\/\/doi.org\/10.1145\/2564926","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"type":"print","value":"1550-4832"},{"type":"electronic","value":"1550-4840"}],"subject":[],"published":{"date-parts":[[2014,2]]},"assertion":[{"value":"2011-11-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2012-07-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2014-03-06","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}