{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:52:14Z","timestamp":1750308734394,"version":"3.41.0"},"reference-count":33,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2014,2,1]],"date-time":"2014-02-01T00:00:00Z","timestamp":1391212800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100002920","name":"Research Grants Council, University Grants Committee, Hong Kong","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100002920","id-type":"DOI","asserted-by":"publisher"}]},{"name":"DAG"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2014,2]]},"abstract":"<jats:p>As transistor density continues to increase with the advent of nanotechnology, reliability issues raised by the more frequent appearance of soft errors are becoming critical for future embedded multiprocessor systems design. State-of-the-art techniques for soft error protections targeting multiprocessor systems result either high chip cost and area overhead or high performance degradation and energy consumption, and do not fulfill the increasing requirements for high performance and dependability. In this article we present a systematic approach, that is, the Sensor Networks-on-Chip (SENoC), to collaboratively and efficiently manage on-chip applications and overcome reliability threats to Multiprocessor Systems-on-Chip (MPSoC). A hardware-software collaborative approach is proposed to solve soft error problems: a hardware-based on-chip sensor network is built for soft error detection, and a software-based recovery mechanism is applied for soft error correction. A two-step scheduling scheme is presented for reliable application and chip management, combining an off-line static optimization stage for application performance maximization and an online lightweight dynamic adjustment stage to handle runtime variations and exceptions. This strategy introduces only trivial overhead on hardware design and much lower overhead on software control and execution, and hence performance degradation and energy consumption is greatly reduced. We build a cycle-accurate simulator using SystemC, and verify the effectiveness of our technique by comparing performance with related techniques on several real-world applications.<\/jats:p>","DOI":"10.1145\/2564928","type":"journal-article","created":{"date-parts":[[2014,3,4]],"date-time":"2014-03-04T13:24:59Z","timestamp":1393939499000},"page":"1-20","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip"],"prefix":"10.1145","volume":"10","author":[{"given":"Weichen","family":"Liu","sequence":"first","affiliation":[{"name":"The Hong Kong University of Science and Technology, Hong Kong"}]},{"given":"Xuan","family":"Wang","sequence":"additional","affiliation":[{"name":"The Hong Kong University of Science and Technology, Hong Kong"}]},{"given":"Jiang","family":"Xu","sequence":"additional","affiliation":[{"name":"The Hong Kong University of Science and Technology, Hong Kong"}]},{"given":"Wei","family":"Zhang","sequence":"additional","affiliation":[{"name":"Nanyang Technological University, Singapore"}]},{"given":"Yaoyao","family":"Ye","sequence":"additional","affiliation":[{"name":"The Hong Kong University of Science and Technology, Hong Kong"}]},{"given":"Xiaowen","family":"Wu","sequence":"additional","affiliation":[{"name":"The Hong Kong University of Science and Technology, Hong Kong"}]},{"given":"Mahdi","family":"Nikdast","sequence":"additional","affiliation":[{"name":"The Hong Kong University of Science and Technology, Hong Kong"}]},{"given":"Zhehui","family":"Wang","sequence":"additional","affiliation":[{"name":"The Hong Kong University of Science and Technology, Hong Kong"}]}],"member":"320","published-online":{"date-parts":[[2014,3,6]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"http:\/\/www.systemc.org.  http:\/\/www.systemc.org."},{"key":"e_1_2_1_2_1","unstructured":"http:\/\/www.synopsys.com.  http:\/\/www.synopsys.com."},{"key":"e_1_2_1_3_1","unstructured":"http:\/\/www.cadence.com.  http:\/\/www.cadence.com."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.523.0285"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2005.69"},{"volume-title":"Proceedings of the IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, IEEE Computer Society, Washington, D.C., 3--11","author":"Dutta A","key":"e_1_2_1_6_1","unstructured":"A Dutta . and N. A. Touba . 2007. Reliable network-on-chip using a low cost unequal error protection code . In Proceedings of the IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, IEEE Computer Society, Washington, D.C., 3--11 . A Dutta. and N. A. Touba. 2007. Reliable network-on-chip using a low cost unequal error protection code. In Proceedings of the IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, IEEE Computer Society, Washington, D.C., 3--11."},{"volume-title":"Proceedings of the 36th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO 36)","author":"Ernst D.","key":"e_1_2_1_7_1","unstructured":"D. Ernst , N. S. Kim , S. Das , S. Pant , R. Rao , T. Pham , C. Ziesler , D. Blaauw , T. Austin , K. Flautner , and T. Mudge . 2003. Razor: A low-power pipeline based on circuit-level timing speculation . In Proceedings of the 36th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO 36) , IEEE Computer Society, Washington, D.C., 7. D. Ernst, N. S. Kim, S. Das, S. Pant, R. Rao, T. Pham, C. Ziesler, D. Blaauw, T. Austin, K. Flautner, and T. Mudge. 2003. Razor: A low-power pipeline based on circuit-level timing speculation. In Proceedings of the 36th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO 36), IEEE Computer Society, Washington, D.C., 7."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2007.128"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/71.584093"},{"volume-title":"Proceedings of the Conference on Design, Automation and Test in Europe (DATE'09)","author":"Izosimov V.","key":"e_1_2_1_10_1","unstructured":"V. Izosimov , I. Polian , P. Pop , P. Eles , and Z. Peng . 2009. Analysis and optimization of fault-tolerant embedded systems with hardened processors . In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'09) , IEEE Computer Society, Washington, D.C., 682--687. V. Izosimov, I. Polian, P. Pop, P. Eles, and Z. Peng. 2009. Analysis and optimization of fault-tolerant embedded systems with hardened processors. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'09), IEEE Computer Society, Washington, D.C., 682--687."},{"key":"e_1_2_1_11_1","unstructured":"JEDEC Standard JESD89. 2001. http:\/\/www.jedec.org.  JEDEC Standard JESD89. 2001. http:\/\/www.jedec.org."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2010.204"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2011.49"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/71.735960"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065648"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403603"},{"volume-title":"Proceedings of the IEEE International Test Conference (ITC'06)","author":"Mitra S.","key":"e_1_2_1_17_1","unstructured":"S. Mitra , M. Zhang , S. Waqas , N. Seifert , B. Gill , and K. S. Kim . 2006. Combinational logic soft error correction . In Proceedings of the IEEE International Test Conference (ITC'06) , IEEE Computer Society, Washington, D.C., 1--9. S. Mitra, M. Zhang, S. Waqas, N. Seifert, B. Gill, and K. S. Kim. 2006. Combinational logic soft error correction. In Proceedings of the IEEE International Test Conference (ITC'06), IEEE Computer Society, Washington, D.C., 1--9."},{"key":"e_1_2_1_18_1","volume-title":"Proceedings of the 49th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS'06)","volume":"1","author":"Naseer R.","unstructured":"R. Naseer , R. Z. Bhatti , and J. Draper . 2006. Analysis of soft error mitigation techniques for register files in IBM CU-08 90nm technology . In Proceedings of the 49th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS'06) , vol. 1 , IEEE Computer Society, Washington, D.C., 515--519. R. Naseer, R. Z. Bhatti, and J. Draper. 2006. Analysis of soft error mitigation techniques for register files in IBM CU-08 90nm technology. In Proceedings of the 49th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS'06), vol. 1, IEEE Computer Society, Washington, D.C., 515--519."},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.5555\/832299.836499"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2005.855790"},{"volume-title":"Proceedings of the 15th Symposium on Integrated Circuits and Systems Design (SBCCI'02)","author":"Nicolescu B.","key":"e_1_2_1_21_1","unstructured":"B. Nicolescu , R. Velazco , M. Sonza-Reorda , M. Rebaudengo , and M. Violante . 2002. A software fault tolerance method for safety-critical systems: Effectiveness and drawbacks . In Proceedings of the 15th Symposium on Integrated Circuits and Systems Design (SBCCI'02) , IEEE Computer Society, Washington, D.C., 101. B. Nicolescu, R. Velazco, M. Sonza-Reorda, M. Rebaudengo, and M. Violante. 2002. A software fault tolerance method for safety-critical systems: Effectiveness and drawbacks. In Proceedings of the 15th Symposium on Integrated Circuits and Systems Design (SBCCI'02), IEEE Computer Society, Washington, D.C., 101."},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2006.35"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/PRDC.2007.9"},{"key":"e_1_2_1_24_1","unstructured":"D. K. Pradhan (Ed.). 1996. Fault-Tolerant Computer System Design. Prentice-Hall Upper Saddle River NJ.   D. K. Pradhan (Ed.). 1996. Fault-Tolerant Computer System Design. Prentice-Hall Upper Saddle River NJ."},{"volume-title":"Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'99)","author":"Rebaudengo M.","key":"e_1_2_1_25_1","unstructured":"M. Rebaudengo , M. S. Reorda , M. Torchiano , and M. Violante . 1999. Soft-error detection through software fault-tolerance techniques . In Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'99) , IEEE Computer Society, Washington, D.C., 210--218. M. Rebaudengo, M. S. Reorda, M. Torchiano, and M. Violante. 1999. Soft-error detection through software fault-tolerance techniques. In Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'99), IEEE Computer Society, Washington, D.C., 210--218."},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2005.34"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2158100"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2007.5"},{"volume-title":"Proceedings of the Conference on Design, Automation and Test in Europe (DATE'07)","author":"Seshia S. A.","key":"e_1_2_1_29_1","unstructured":"S. A. Seshia , W. Li , and S. Mitra . 2007. Verification-guided soft error resilience . In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'07) , EDA Consortium, 1442--1447. S. A. Seshia, W. Li, and S. Mitra. 2007. Verification-guided soft error resilience. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'07), EDA Consortium, 1442--1447."},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.42"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1002\/jos.116"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629395.1629430"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1146926"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2564928","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2564928","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T20:22:00Z","timestamp":1750278120000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2564928"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,2]]},"references-count":33,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2014,2]]}},"alternative-id":["10.1145\/2564928"],"URL":"https:\/\/doi.org\/10.1145\/2564928","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"type":"print","value":"1550-4832"},{"type":"electronic","value":"1550-4840"}],"subject":[],"published":{"date-parts":[[2014,2]]},"assertion":[{"value":"2011-09-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2012-11-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2014-03-06","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}