{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:17:56Z","timestamp":1750306676371,"version":"3.41.0"},"reference-count":24,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2014,3,1]],"date-time":"2014-03-01T00:00:00Z","timestamp":1393632000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Altera"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2014,3]]},"abstract":"FPGA technology is commonly used to prototype new digital designs before entering fabrication. Whilst these physical prototypes can operate many orders of magnitude faster than through a logic simulator, a fundamental limitation is their lack of on-chip visibility when debugging. To counter this, trace-buffer-based instrumentation can be installed into the prototype, allowing designers to capture a predetermined window of signal data during live operation for offline analysis. However, instead of requiring the designer to recompile their entire circuit every time the window is modified, this article proposes that an overlay network is constructed using only spare FPGA routing multiplexers to connect all circuit signals through to the trace instruments. Thus, during debugging, designers would only need to reconfigure this network instead of finding a new place-and-route solution. Furthermore, we describe how this network can deliver signals to both the trigger and trace units of these instruments, which are implemented simultaneously using dual-port RAMs. Our results show that new network configurations connecting any subset of signals to 80--90% of the available RAM capacity can be computed in less than 70 seconds, for a 100,000 LUT circuit, as many times as necessary. Our tool\u2014QuickTrace\u2014is available for download.<\/jats:p>","DOI":"10.1145\/2566668","type":"journal-article","created":{"date-parts":[[2014,3,24]],"date-time":"2014-03-24T13:45:50Z","timestamp":1395668750000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["Accelerating FPGA debug"],"prefix":"10.1145","volume":"19","author":[{"given":"Eddie","family":"Hung","sequence":"first","affiliation":[{"name":"University of British Columbia, Vancouver, BC, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Steven J. E.","family":"Wilton","sequence":"additional","affiliation":[{"name":"University of British Columbia, Vancouver, BC, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2014,3,28]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"Altera. 2012. Quartus II Handbook Version 12.1 Volume 3: Verification. http:\/\/www.altera.com\/literature\/hb\/qts\/qts\_qii5v3.pdf. (November 2012). Altera. 2012. Quartus II Handbook Version 12.1 Volume 3: Verification. http:\/\/www.altera.com\/literature\/hb\/qts\/qts\_qii5v3.pdf. (November 2012)."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145720"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.entcs.2011.06.003"},{"key":"e_1_2_1_4_1","unstructured":"Free Software Foundation. 2013. GCC 4.8 Release Series: Changes New Features and Fixes. http:\/\/gcc.gnu.org\/gcc-4.8\/changes.html. (February 2013). Free Software Foundation. 2013. GCC 4.8 Release Series: Changes New Features and Fixes. http:\/\/gcc.gnu.org\/gcc-4.8\/changes.html. (February 2013)."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.5555\/1058426.1058867"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2013.40"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2011.103"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2435264.2435272"},{"key":"e_1_2_1_9_1","article-title":"Incremental trace-buffer insertion for FPGA debug","author":"Hung Eddie","year":"2012","journal-title":"IEEE Trans. VLSI Syst. To appear. http:\/\/ieeexplore.ieee.org\/xpls\/abs\_all.jsp?arnumber=6510525."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2011.102"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2009158"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2189395"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/201310.201328"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145738"},{"volume-title":"Proceedings of the IEEE International Conference on Field Programmable Technology. 241--247","author":"Quinton B.","key":"e_1_2_1_15_1"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145708"},{"volume-title":"Identify: Simulator-like Visibility into Hardware Debug","year":"2010","key":"e_1_2_1_17_1"},{"key":"e_1_2_1_18_1","unstructured":"Steve Teig. 2012. Programmable logic devices in 2032? In Proceedings of the FPGA2012 Pre-Conference Workshop. http:\/\/tcfpga.org\/fpga2012\/SteveTeig.pdf. (February 2012). Steve Teig. 2012. Programmable logic devices in 2032? In Proceedings of the FPGA2012 Pre-Conference Workshop. http:\/\/tcfpga.org\/fpga2012\/SteveTeig.pdf. (February 2012)."},{"key":"e_1_2_1_19_1","unstructured":"Tektronix. 2012. Certus Debug Suite. http:\/\/www.tek.com\/sites\/tek.com\/files\/media\/media\/resources\/Certus\_Debug\_Suite\_Datasheet\_54W-28030-1\_4.pdf. (July 2012). Tektronix. 2012. Certus Debug Suite. http:\/\/www.tek.com\/sites\/tek.com\/files\/media\/media\/resources\/Certus\_Debug\_Suite\_Datasheet\_54W-28030-1\_4.pdf. (July 2012)."},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.5555\/647928.739887"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275137"},{"key":"e_1_2_1_22_1","unstructured":"Mike Wirthlin Brent Nelson Brad Hutchings Peter Athanas and Shawn Bohner. 2008. FPGA design productivity: Existing limitations and root causes. http:\/\/www.chrec.org\/ftsw\/FDP\_Session1\_Posted.pdf. (June 2008). Mike Wirthlin Brent Nelson Brad Hutchings Peter Athanas and Shawn Bohner. 2008. FPGA design productivity: Existing limitations and root causes. http:\/\/www.chrec.org\/ftsw\/FDP\_Session1\_Posted.pdf. (June 2008)."},{"key":"e_1_2_1_23_1","unstructured":"Xilinx. 2011. Virtex-6 FPGA Memory Resources: User Guide (UG363 v1.6). http:\/\/www.xilinx.com\/support\/documentation\/user\_guides\/ug363.pdf. (April 2011). Xilinx. 2011. Virtex-6 FPGA Memory Resources: User Guide (UG363 v1.6). http:\/\/www.xilinx.com\/support\/documentation\/user\_guides\/ug363.pdf. (April 2011)."},{"key":"e_1_2_1_24_1","unstructured":"Xilinx. 2012. ChipScope Pro Software and Cores User Guide UG029 (v14.3). http:\/\/www.xilinx.com\/support\/documentation\/sw\_manuals\/xilinx14\_4\/chipscope\_pro\_sw\_cores\_ug029.pdf. (October 2012). Xilinx. 2012. ChipScope Pro Software and Cores User Guide UG029 (v14.3). http:\/\/www.xilinx.com\/support\/documentation\/sw\_manuals\/xilinx14\_4\/chipscope\_pro\_sw\_cores\_ug029.pdf. (October 2012)."}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2566668","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2566668","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T07:01:01Z","timestamp":1750230061000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2566668"}},"subtitle":["Increasing visibility using a runtime reconfigurable observation and triggering network"],"short-title":[],"issued":{"date-parts":[[2014,3]]},"references-count":24,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2014,3]]}},"alternative-id":["10.1145\/2566668"],"URL":"https:\/\/doi.org\/10.1145\/2566668","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"type":"print","value":"1084-4309"},{"type":"electronic","value":"1557-7309"}],"subject":[],"published":{"date-parts":[[2014,3]]},"assertion":[{"value":"2013-06-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2013-12-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2014-03-28","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}