{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:19:57Z","timestamp":1750306797814,"version":"3.41.0"},"reference-count":22,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2014,4,1]],"date-time":"2014-04-01T00:00:00Z","timestamp":1396310400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","award":["2010-HJ-2079"],"award-info":[{"award-number":["2010-HJ-2079"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2014,4]]},"abstract":"<jats:p>\n            Recently, multigate transistors have been gaining attention as an alternative to conventional MOSFETs. Superior gate control over the channel, smaller subthreshold leakage, and reduced susceptibility to process variations are some of the key features that give multigate structures a competitive edge over MOSFETs. Among various multigate structures, silicon-on-insulator (SOI) FinFETs are promising, owing to their ease of fabrication. However, characterization of SOI FinFET devices\/gates needs immediate attention in order for them to gain greater popularity in this decade. Ideally, 3D device simulation should be done for accurate circuit analysis. However, this is impractical due to the huge CPU time required. As a possible alternative, simulating a 2D crosssection of the device yields 10\u00d7 to 100\u00d7 reduction in CPU time. However, this introduces significant error in the range of 7% to 20% when evaluating the on\/off current (\n            <jats:italic>\n              I\n              <jats:sub>ON<\/jats:sub>\n              \/I\n              <jats:sub>OFF<\/jats:sub>\n            <\/jats:italic>\n            ) for a single device and leakage current or propagation delay (\n            <jats:italic>\n              I\n              <jats:sub>LEAK<\/jats:sub>\n              \/t\n              <jats:sub>D<\/jats:sub>\n            <\/jats:italic>\n            ) for logic gates.\n          <\/jats:p>\n          <jats:p>\n            In this work, we first present a methodology to obtain optimized 3D device simulation models for SOI FinFETs. Based on these 3D models, we develop adjusted 2D models to capture 3D simulation accuracy with 2D simulation efficiency. We report results for the 22nm SOI FinFET technology node. We adjust gate underlap (\n            <jats:italic>\n              L\n              <jats:sub>UN<\/jats:sub>\n            <\/jats:italic>\n            ) in the 2D cross section of the n\/pFinFET devices in order to mimic 3D device behavior. When the adjusted 2D models are employed in mixed-mode simulation of FinFET logic gates, the error in the evaluation of\n            <jats:italic>\n              I\n              <jats:sub>LEAK<\/jats:sub>\n              \/t\n              <jats:sub>D<\/jats:sub>\n            <\/jats:italic>\n            is very small. To the best of our knowledge, this is the first such attempt. We show that 2D device models remain valid even under process, voltage, and temperature (PVT) variations. We target process variations in gate length (\n            <jats:italic>\n              L\n              <jats:sub>G<\/jats:sub>\n            <\/jats:italic>\n            ), fin thickness (\n            <jats:italic>\n              T\n              <jats:sub>SI<\/jats:sub>\n            <\/jats:italic>\n            ), gate oxide thickness (\n            <jats:italic>\n              T\n              <jats:sub>OX<\/jats:sub>\n            <\/jats:italic>\n            ), and gate workfunction (\n            <jats:italic>\n              \u03a6\n              <jats:sub>G<\/jats:sub>\n            <\/jats:italic>\n            ), which are the parameters that have been shown to have the most impact on leakage and delay.\n          <\/jats:p>","DOI":"10.1145\/2567670","type":"journal-article","created":{"date-parts":[[2014,5,2]],"date-time":"2014-05-02T13:45:52Z","timestamp":1399038352000},"page":"1-19","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":11,"title":["3D vs. 2D Device Simulation of FinFET Logic Gates under PVT Variations"],"prefix":"10.1145","volume":"10","author":[{"given":"Sourindra M.","family":"Chaudhuri","sequence":"first","affiliation":[{"name":"Princeton University, Princeton, NJ"}]},{"given":"Niraj K.","family":"Jha","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ"}]}],"member":"320","published-online":{"date-parts":[[2014,5,6]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2040094"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147020"},{"volume-title":"Proceedings of the IEEE International Symposium on Quality Electronic Design. 1--8.","author":"Bhoj A. N.","key":"e_1_2_1_3_1","unstructured":"A. N. Bhoj and N. K. Jha . 2011. Design of ultra-low-leakage logic gates and flip-flops in high-performance FinFET technology . In Proceedings of the IEEE International Symposium on Quality Electronic Design. 1--8. A. N. Bhoj and N. K. Jha. 2011. Design of ultra-low-leakage logic gates and flip-flops in high-performance FinFET technology. In Proceedings of the IEEE International Symposium on Quality Electronic Design. 1--8."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2011.6081437"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2005.856191"},{"volume-title":"Proceedings of the International Conference on Computer-Aided Design. 747--751","author":"Choi J. H.","key":"e_1_2_1_6_1","unstructured":"J. H. Choi , J. Murthy , and K. Roy . 2007. The effect of process variation on device temperatures in FinFET circuits . In Proceedings of the International Conference on Computer-Aided Design. 747--751 . J. H. Choi, J. Murthy, and K. Roy. 2007. The effect of process variation on device temperatures in FinFET circuits. In Proceedings of the International Conference on Computer-Aided Design. 747--751."},{"volume-title":"FinFETs and Other Multi-Gate Transistors","author":"Colinge J. P.","key":"e_1_2_1_7_1","unstructured":"J. P. Colinge . 2007. FinFETs and Other Multi-Gate Transistors . Springer , New York, NY . J. P. Colinge. 2007. FinFETs and Other Multi-Gate Transistors. Springer, New York, NY."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.909809"},{"key":"e_1_2_1_9_1","series-title":"Series 107, 1","volume-title":"Physics: Conf","author":"Khan H. R.","year":"2008","unstructured":"H. R. Khan , D. Mamaluy , and D. Vasileska . 2008 . 3D NEGF quantum transport simulator for modeling ballistic transport in nano FinFETs . Physics: Conf . Series 107, 1 (2008). H. R. Khan, D. Mamaluy, and D. Vasileska. 2008. 3D NEGF quantum transport simulator for modeling ballistic transport in nano FinFETs. Physics: Conf. Series 107, 1 (2008)."},{"volume-title":"Proceedings of the IEEE International SOI Conference.","author":"Kumar A.","key":"e_1_2_1_10_1","unstructured":"A. Kumar , B. A. Minch , and S. Tiwari . 2004. Low voltage and performance tunable CMOS circuit design using independently driven double gate MOSFETs . In Proceedings of the IEEE International SOI Conference. A. Kumar, B. A. Minch, and S. Tiwari. 2004. Low voltage and performance tunable CMOS circuit design using independently driven double gate MOSFETs. In Proceedings of the IEEE International SOI Conference."},{"volume-title":"Proceedings of the IEEE International Symposium on Quality Electronic Design.","author":"Mishra P.","key":"e_1_2_1_11_1","unstructured":"P. Mishra , A. N. Bhoj , and N. K. Jha . 2010. Die-level leakage power analysis of FinFET circuits considering process variations . In Proceedings of the IEEE International Symposium on Quality Electronic Design. P. Mishra, A. N. Bhoj, and N. K. Jha. 2010. Die-level leakage power analysis of FinFET circuits considering process variations. In Proceedings of the IEEE International Symposium on Quality Electronic Design."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1543438.1543440"},{"volume-title":"Proceedings of the IEEE International Conference on Computer Design. 560--567","author":"Muttreja A.","key":"e_1_2_1_13_1","unstructured":"A. Muttreja , N. Agarwal , and N. K. Jha . 2007. CMOS logic design with independent-gate FinFETs . In Proceedings of the IEEE International Conference on Computer Design. 560--567 . A. Muttreja, N. Agarwal, and N. K. Jha. 2007. CMOS logic design with independent-gate FinFETs. In Proceedings of the IEEE International Conference on Computer Design. 560--567."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCD.2004.1263404"},{"volume-title":"Proceedings of the IEEE International SOC Conference. 211--214","author":"Ouyang J.","key":"e_1_2_1_15_1","unstructured":"J. Ouyang and Y. Xie . 2008. Power optimization for FinFET based circuits using genetic algorithms . In Proceedings of the IEEE International SOC Conference. 211--214 . J. Ouyang and Y. Xie. 2008. Power optimization for FinFET based circuits using genetic algorithms. In Proceedings of the IEEE International SOC Conference. 211--214."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2097310"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2005.04.017"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.79"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147047"},{"key":"e_1_2_1_20_1","unstructured":"Synopsys. 2011. Sentaurus TCAD Manual. (2011). http:\/\/www.synopsys.com.  Synopsys. 2011. Sentaurus TCAD Manual. (2011). http:\/\/www.synopsys.com."},{"volume-title":"Proceedings of the International Conference on Microelectronics. 175--178","author":"Tawfik S. A.","key":"e_1_2_1_21_1","unstructured":"S. A. Tawfik and V. Kursun . 2007. High speed FinFET domino logic circuits using independent gate-biased double-gate keepers providing dynamically adjusted immunity to noise . In Proceedings of the International Conference on Microelectronics. 175--178 . S. A. Tawfik and V. Kursun. 2007. High speed FinFET domino logic circuits using independent gate-biased double-gate keepers providing dynamically adjusted immunity to noise. In Proceedings of the International Conference on Microelectronics. 175--178."},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2003.818594"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2567670","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2567670","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T07:34:39Z","timestamp":1750232079000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2567670"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,4]]},"references-count":22,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2014,4]]}},"alternative-id":["10.1145\/2567670"],"URL":"https:\/\/doi.org\/10.1145\/2567670","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"type":"print","value":"1550-4832"},{"type":"electronic","value":"1550-4840"}],"subject":[],"published":{"date-parts":[[2014,4]]},"assertion":[{"value":"2012-09-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2013-08-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2014-05-06","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}