{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,24]],"date-time":"2025-10-24T16:45:12Z","timestamp":1761324312271,"version":"3.41.0"},"reference-count":17,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2014,1,1]],"date-time":"2014-01-01T00:00:00Z","timestamp":1388534400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["Queue"],"published-print":{"date-parts":[[2014,1]]},"abstract":"<jats:p>Multithreaded applications take advantage of increasing core counts to achieve high performance. Such programs, however, typically require programmers to reason about data shared among multiple threads. Programmers use synchronization mechanisms such as mutual-exclusion locks to ensure correct updates to shared data in the presence of accesses from multiple threads. Unfortunately, these mechanisms serialize thread accesses to the data and limit scalability.<\/jats:p>","DOI":"10.1145\/2576966.2579227","type":"journal-article","created":{"date-parts":[[2020,9,3]],"date-time":"2020-09-03T03:52:06Z","timestamp":1599105126000},"page":"20-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["Scaling Existing Lock-based Applications with Lock Elision"],"prefix":"10.1145","volume":"12","author":[{"given":"Andi","family":"Kleen","sequence":"first","affiliation":[{"name":"Intel Corporation"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2014,1,8]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1400214.1400228"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950373"},{"volume-title":"The 3rd Annual ACM SIGPLAN Workshop on Transactional Computing.","year":"2008","author":"Dice D.","key":"e_1_2_1_3_1"},{"key":"e_1_2_1_4_1","unstructured":"GCC. 2013. X86 transaction memory intrinsics; http:\/\/gcc.gnu.org\/onlinedocs\/gcc-4.8.2\/gcc\/X86-transactional-memory-intrinsics.html#X86-transactional-memory-intrinsics.  GCC. 2013. X86 transaction memory intrinsics; http:\/\/gcc.gnu.org\/onlinedocs\/gcc-4.8.2\/gcc\/X86-transactional-memory-intrinsics.html#X86-transactional-memory-intrinsics."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165164"},{"key":"e_1_2_1_6_1","unstructured":"IBM. 2013. Power ISA; http:\/\/www.power.org\/documentation\/power-isa-version-2-07\/.  IBM. 2013. Power ISA; http:\/\/www.power.org\/documentation\/power-isa-version-2-07\/."},{"key":"e_1_2_1_7_1","unstructured":"Intel. 2012. Intel 64 and IA-32 Architectures Software Developer Manuals Volume 1 Chapter 14; http:\/\/www.intel.com\/content\/www\/us\/en\/processors\/architectures-software-developer-manuals.html.  Intel. 2012. Intel 64 and IA-32 Architectures Software Developer Manuals Volume 1 Chapter 14; http:\/\/www.intel.com\/content\/www\/us\/en\/processors\/architectures-software-developer-manuals.html."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.12"},{"key":"e_1_2_1_9_1","unstructured":"Kleen A. 2013. tsx-tools; http:\/\/github.com\/andikleen\/tsx-tools.  Kleen A. 2013. tsx-tools; http:\/\/github.com\/andikleen\/tsx-tools."},{"key":"e_1_2_1_10_1","unstructured":"McKenney P. E. 2013. Is parallel programming hard and if so what can you do about it?; https:\/\/www.kernel.org\/pub\/linux\/kernel\/people\/paulmck\/perfbook\/perfbook.html  McKenney P. E. 2013. Is parallel programming hard and if so what can you do about it?; https:\/\/www.kernel.org\/pub\/linux\/kernel\/people\/paulmck\/perfbook\/perfbook.html"},{"key":"e_1_2_1_11_1","unstructured":"McVoy L. 1999. SMP scaling considered harmful; http:\/\/www.bitmover.com\/llnl\/smp.pdf.  McVoy L. 1999. SMP scaling considered harmful; http:\/\/www.bitmover.com\/llnl\/smp.pdf."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/2500468.2500476"},{"volume-title":"the Sixth Annual ACM SIGPLAN Workshop on Transactional Computing.","year":"2011","author":"Pohlack M.","key":"e_1_2_1_13_1"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/563998.564036"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2009.20"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370836"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/2503210.2503232"}],"container-title":["Queue"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2576966.2579227","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2576966.2579227","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T06:55:54Z","timestamp":1750229754000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2576966.2579227"}},"subtitle":["Lock elision enables existing lock-based programs to achieve the performance benefits of nonblocking synchronization and fine-grain locking with minor software engineering effort."],"short-title":[],"issued":{"date-parts":[[2014,1]]},"references-count":17,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2014,1]]}},"alternative-id":["10.1145\/2576966.2579227"],"URL":"https:\/\/doi.org\/10.1145\/2576966.2579227","relation":{},"ISSN":["1542-7730","1542-7749"],"issn-type":[{"type":"print","value":"1542-7730"},{"type":"electronic","value":"1542-7749"}],"subject":[],"published":{"date-parts":[[2014,1]]},"assertion":[{"value":"2014-01-08","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}