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Refresh operations contend with read operations, which increases read latency and reduces system performance. We show that eliminating latency penalty due to refresh can improve average performance by 7.2%. However, simply doing intelligent scheduling of refresh operations is ineffective at obtaining significant performance improvement.<\/jats:p>\n          <jats:p>\n            This article provides an alternative and scalable option to reduce the latency penalty due to refresh. It exploits the property that each refresh operation in a typical DRAM device internally refreshes multiple DRAM rows in JEDEC-based distributed refresh mode. Therefore, a refresh operation has well-defined points at which it can potentially be\n            <jats:italic>Paused<\/jats:italic>\n            to service a pending read request. Leveraging this property, we propose\n            <jats:italic>Refresh Pausing<\/jats:italic>\n            , a solution that is highly effective at alleviating the contention from refresh operations. It provides an average performance improvement of 5.1% for 8Gb devices and becomes even more effective for future high-density technologies. We also show that Refresh Pausing significantly outperforms the recently proposed Elastic Refresh scheme.\n          <\/jats:p>","DOI":"10.1145\/2579669","type":"journal-article","created":{"date-parts":[[2014,4,1]],"date-time":"2014-04-01T13:06:54Z","timestamp":1396357614000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":26,"title":["Refresh pausing in DRAM memory systems"],"prefix":"10.1145","volume":"11","author":[{"given":"Prashant J.","family":"Nair","sequence":"first","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA"}]},{"given":"Chia-Chen","family":"Chou","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA"}]},{"given":"Moinuddin K.","family":"Qureshi","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA"}]}],"member":"320","published-online":{"date-parts":[[2014,2]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"USIMM: The Utah SImulated Memory Module. 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