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Archit. Code Optim."],"published-print":{"date-parts":[[2014,2]]},"abstract":"<jats:p>Nonvolatile memories (NVMs) have the potential to replace low-level SRAM or eDRAM on-chip caches because NVMs save standby power and provide large cache capacity. However, limited write endurance is a common problem for NVM technologies, and today's cache management might result in unbalanced cache write traffic, causing heavily written cache blocks to fail much earlier than others. Although wear-leveling techniques for NVM-based main memories exist, we cannot simply apply them to NVM-based caches. This is because cache writes have intraset variations as well as interset variations, while writes to main memories only have interset variations.<\/jats:p>\n          <jats:p>\n            To solve this problem, we propose i\n            <jats:sup>2<\/jats:sup>\n            WAP, a new cache management policy that can reduce both inter- and intraset write variations. i\n            <jats:sup>2<\/jats:sup>\n            WAP has two features: Swap-Shift, an enhancement based on existing main memory wear leveling to reduce cache interset write variations, and Probabilistic Set Line Flush, a novel technique to reduce cache intraset write variations. Implementing i\n            <jats:sup>2<\/jats:sup>\n            WAP only needs two global counters and two global registers. In one of our studies, i\n            <jats:sup>2<\/jats:sup>\n            WAP can improve the NVM cache lifetime by 75% on average and up to 224%. We also validate that i\n            <jats:sup>2<\/jats:sup>\n            WAP is effective in systems with different cache configurations and workloads.\n          <\/jats:p>","DOI":"10.1145\/2579671","type":"journal-article","created":{"date-parts":[[2014,3,18]],"date-time":"2014-03-18T12:09:07Z","timestamp":1395144547000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":14,"title":["Endurance-aware cache line management for non-volatile caches"],"prefix":"10.1145","volume":"11","author":[{"given":"Jue","family":"Wang","sequence":"first","affiliation":[{"name":"Pennsylvania State University, University Park, PA"}]},{"given":"Xiangyu","family":"Dong","sequence":"additional","affiliation":[{"name":"Qualcomm Technology, Inc., San Diego, CA"}]},{"given":"Yuan","family":"Xie","sequence":"additional","affiliation":[{"name":"Pennsylvania State University, University Park, PA"}]},{"given":"Norman P.","family":"Jouppi","sequence":"additional","affiliation":[{"name":"Hewlett-Packard Labs, Mountain View, CA"}]}],"member":"320","published-online":{"date-parts":[[2014,2]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Proceedings of the USENIX Conference on Hot Topics in Storage and File Systems. 2--6.","author":"Akel A.","year":"2011","unstructured":"A. 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Energy- and endurance-aware design of phase change memory caches . In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition. 136--141 . Y. Joo, D. Niu, X. Dong, et al. 2010. Energy- and endurance-aware design of phase change memory caches. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition. 136--141."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/871506.871511"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2220791"},{"volume-title":"Proceedings of the International Reliability Physics Symposium. 157--162","author":"Kim K.","key":"e_1_2_1_16_1","unstructured":"K. Kim and S. J. Ahn . 2005. Reliability investigations for manufacturable high density PRAM . In Proceedings of the International Reliability Physics Symposium. 157--162 . K. Kim and S. J. Ahn. 2005. Reliability investigations for manufacturable high density PRAM. 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