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Syst."],"published-print":{"date-parts":[[2014,7]]},"abstract":"<jats:p>On-chip temperatures continue to rise, in spite of design efforts towards more efficient cooling and novel low-power technologies. Run-time thermal management techniques, such as speed scaling and system throttling, constitute a standard component in today's processors. One such technique is the feedback control of the processing speed based on the on-chip temperature. If suitably designed, such a controller can ensure that the temperature of the processor does not exceed a given bound, independent of the application. Such isolation of needs is encouraging. However, from the application's stand-point, such a processor must provide performance guarantees; in particular, the guarantee that real-time jobs do not have worst-case delays larger than their relative deadlines. For applications which exhibit variability, such as bursty arrival patterns, computing such guarantees is not apparent. As key enablers in such a computation, for the specific setting of First-Come-First-Serve (FCFS) scheduling, we (a) define and prove a monotonicity principle satisfied by the processor with the said controller, and (b) propose a thermally clipped processor model. We identify the worst-case trace simulating which on a suitably chosen thermally clipped processor provides the tight upper-bound on the worst-case delay. These results hold for general models of (a) the power consumption of the processor, (b) its thermal model, (c) the speed scaling law, and (d) the task model. For this modelling scope, we show that the same worst-case trace also leads to the worst-case temperature of the processor. This is useful to characterise tasks which do not load the processor sufficiently to hit the given peak temperature bound. We demonstrate the utility of this calculation by designing a shaper to delay the arrival times of jobs and thereby restrict the observed worst-case temperature while still meeting the task's deadlines.<\/jats:p>","DOI":"10.1145\/2584611","type":"journal-article","created":{"date-parts":[[2014,4,8]],"date-time":"2014-04-08T12:24:20Z","timestamp":1396959860000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Worst-case guarantees on a processor with temperature-based feedback control of speed"],"prefix":"10.1145","volume":"13","author":[{"given":"Pratyush","family":"Kumar","sequence":"first","affiliation":[{"name":"ETH Zurich, Zurich, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lothar","family":"Thiele","sequence":"additional","affiliation":[{"name":"ETH Zurich, Zurich, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2014,4]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/FOCS.2004.24"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.782564"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.5555\/1755809"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/580550.876439"},{"volume-title":"Proceedings of the 12th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 1--12","author":"Paredes S.","key":"e_1_2_1_5_1"},{"key":"e_1_2_1_6_1","unstructured":"Giorgio C. Buttazzo. 1997. Hard Real-Time Computing Systems: Predictable Scheduling Algorithms and Applications. Kluwer Academic Publishers Norwell MA USA.   Giorgio C. Buttazzo. 1997. Hard Real-Time Computing Systems: Predictable Scheduling Algorithms and Applications. Kluwer Academic Publishers Norwell MA USA."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1594233.1594257"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2009.30"},{"key":"e_1_2_1_9_1","unstructured":"Dell. 2007. Managing Data Center Power and Cooling. http:\/\/www.dell.com\/downloads\/global\/power\/ps1q07-20070204-AMD.pdf.  Dell. 2007. Managing Data Center Power and Cooling. http:\/\/www.dell.com\/downloads\/global\/power\/ps1q07-20070204-AMD.pdf."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.876103"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/CCGRID.2007.85"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024835"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/1950815.1950853"},{"key":"e_1_2_1_14_1","unstructured":"Alon Naveh Doron Rajwan Avinash Ananthakrishnan and Eli Weissmann. 2011. Power management architecture of the 2nd generation Intel\u00ae Core microarchitecture formerly codenamed Sandy Bridge. http:\/\/www.hotchips.org\/wp-content\/uploads\/hc_archives\/hc23\/HC23.19.9-Desktop-CPUs\/HC23.19.921.SandyBridge_power_10-Rotem-Intel.pdf.  Alon Naveh Doron Rajwan Avinash Ananthakrishnan and Eli Weissmann. 2011. Power management architecture of the 2nd generation Intel\u00ae Core microarchitecture formerly codenamed Sandy Bridge. http:\/\/www.hotchips.org\/wp-content\/uploads\/hc_archives\/hc23\/HC23.19.9-Desktop-CPUs\/HC23.19.921.SandyBridge_power_10-Rotem-Intel.pdf."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1007\/s00224-007-9070-1"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1165573.1165643"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/MIC.2005.10"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/980152.980157"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/782814.782831"},{"key":"e_1_2_1_20_1","unstructured":"Andrew S. Tanenbaum. 2003. Computer Networks. 4th Ed. Prentice Hall Page 400.  Andrew S. Tanenbaum. 2003. Computer Networks. 4th Ed. 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