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Parallel Comput."],"published-print":{"date-parts":[[2014,10,3]]},"abstract":"<jats:p>Program performance optimization is usually based solely on measurements of execution behavior of code segments using hardware performance counters. However, memory access patterns are critical performance limiting factors for today's multicore chips where performance is highly memory bound. Therefore diagnoses and selection of optimizations based only on measurements of the execution behavior of code segments are incomplete because they do not incorporate knowledge of memory access patterns and behaviors. This article presents a low-overhead tool (MACPO) that captures memory traces and computes metrics for the memory access behavior of source-level (C, C++, Fortran) data structures. MACPO explicitly targets the measurement and metrics important to performance optimization for multicore chips. The article also presents a complete process for integrating measurement and analyses of code execution with measurements and analyses of memory access patterns and behaviors for performance optimization, specifically targeting multicore chips and multichip nodes of clusters. MACPO uses more realistic cache models for computation of latency metrics than those used by previous tools. Evaluation of the effectiveness of adding memory access behavior characteristics of data structures to performance optimization was done on subsets of the ASCI, NAS and Rodinia parallel benchmarks and two versions of one application program from a domain not represented in these benchmarks. Adding characteristics of the behavior of data structures enabled easier diagnoses of bottlenecks and more accurate selection of appropriate optimizations than with only code centric behavior measurements. The performance gains ranged from a few percent to 38 percent.<\/jats:p>","DOI":"10.1145\/2588788","type":"journal-article","created":{"date-parts":[[2014,6,10]],"date-time":"2014-06-10T12:50:17Z","timestamp":1402404617000},"page":"1-20","source":"Crossref","is-referenced-by-count":9,"title":["Enhancing Performance Optimization of Multicore\/Multichip Nodes with Data Structure Metrics"],"prefix":"10.1145","volume":"1","author":[{"given":"Ashay","family":"Rane","sequence":"first","affiliation":[{"name":"University of Texas at Austin"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"James","family":"Browne","sequence":"additional","affiliation":[{"name":"University of Texas at Austin"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2014,5]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Proceedings of the Scalable High Performance Computing Conference. 386--393","author":"Bailey D. H.","unstructured":"D. H. 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Multicore-aware reuse distance analysis. Measurement.  D. L. Schuff B. S. Parsons and V. S. Pai. 2010b. Multicore-aware reuse distance analysis. Measurement .","DOI":"10.1109\/IPDPSW.2010.5470780"},{"key":"e_1_2_1_17_1","volume-title":"Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications.","author":"Sopeju Olalekan A.","year":"2011","unstructured":"Olalekan A. Sopeju , Martin Burtscher , Ashay Rane , and James Browne . 2011 . AutoSCOPE: Automatic suggestions for code optimizations using PerfExpert . In Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications. Olalekan A. Sopeju, Martin Burtscher, Ashay Rane, and James Browne. 2011. AutoSCOPE: Automatic suggestions for code optimizations using PerfExpert. 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Chameleon: A framework for observing, understanding, and imitating the memory behavior of applications. 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