{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:17:20Z","timestamp":1750306640526,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":26,"publisher":"ACM","license":[{"start":{"date-parts":[[2014,5,20]],"date-time":"2014-05-20T00:00:00Z","timestamp":1400544000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2014,5,20]]},"DOI":"10.1145\/2591513.2591541","type":"proceedings-article","created":{"date-parts":[[2014,5,27]],"date-time":"2014-05-27T12:57:10Z","timestamp":1401195430000},"page":"33-38","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":16,"title":["OCV-aware top-level clock tree optimization"],"prefix":"10.1145","author":[{"given":"Tuck-Boon","family":"Chan","sequence":"first","affiliation":[{"name":"University of California San Diego, La Jolla, CA, USA"}]},{"given":"Kwangsoo","family":"Han","sequence":"additional","affiliation":[{"name":"University of California San Diego, La Jolla, CA, USA"}]},{"given":"Andrew B.","family":"Kahng","sequence":"additional","affiliation":[{"name":"University of California San Diego, La Jolla, CA, USA"}]},{"given":"Jae-Gon","family":"Lee","sequence":"additional","affiliation":[{"name":"Samsung Electronics Co., Ltd., Giheung, South Korea"}]},{"given":"Siddhartha","family":"Nath","sequence":"additional","affiliation":[{"name":"University of California San Diego, La Jolla, CA, USA"}]}],"member":"320","published-online":{"date-parts":[[2014,5,20]]},"reference":[{"doi-asserted-by":"publisher","key":"e_1_3_2_1_1_1","DOI":"10.1145\/369691.369699"},{"key":"e_1_3_2_1_2_1","volume-title":"Circuits, Interconnects, and Packaging for VLSI","author":"Bakoglu H. B.","year":"1990","unstructured":"H. B. Bakoglu , Circuits, Interconnects, and Packaging for VLSI . Reading, MA : Addison-Wesley , 1990 . H. B. Bakoglu, Circuits, Interconnects, and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990."},{"key":"e_1_3_2_1_3_1","volume-title":"Static Timing Analysis for Nanometer Designs: A Practical Approach","author":"Bhasker J.","year":"2009","unstructured":"J. Bhasker and R. Chadha , Static Timing Analysis for Nanometer Designs: A Practical Approach , Springer , 2009 . J. Bhasker and R. Chadha, Static Timing Analysis for Nanometer Designs: A Practical Approach, Springer, 2009."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_4_1","DOI":"10.1145\/1837274.1837297"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_5_1","DOI":"10.1145\/566408.566481"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_6_1","DOI":"10.1109\/82.204128"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_7_1","DOI":"10.1145\/157485.165066"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_8_1","DOI":"10.1109\/12.55696"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_9_1","DOI":"10.1109\/5.929649"},{"key":"e_1_3_2_1_10_1","volume-title":"Version 1.0","author":"Kahng A. B.","year":"2000","unstructured":"A. B. Kahng and C.-W. A. Tsao , \" VLSI CAD Software Bookshelf : Bounded-Skew Clock Tree Routing \", Version 1.0 , 2000 . http:\/\/vlsicad.ucsd.edu\/GSRC\/bookshelf\/Slots\/BST\/ A. B. Kahng and C.-W. A. Tsao, \"VLSI CAD Software Bookshelf: Bounded-Skew Clock Tree Routing\", Version 1.0, 2000. http:\/\/vlsicad.ucsd.edu\/GSRC\/bookshelf\/Slots\/BST\/"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_11_1","DOI":"10.1109\/SLIP.2013.6681685"},{"key":"e_1_3_2_1_12_1","first-page":"335","volume-title":"Proc. VLSI-DAT","author":"Lung C.-L.","year":"2010","unstructured":"C.-L. Lung , H.-C. Hsiao , Z.-Y. Zeng and S.-C. Chang , \"LP-Based Multi-Mode Multi-Corner Clock Skew Optimization\" , Proc. VLSI-DAT , 2010 , pp. 335 -- 338 . C.-L. Lung, H.-C. Hsiao, Z.-Y. Zeng and S.-C. Chang, \"LP-Based Multi-Mode Multi-Corner Clock Skew Optimization\", Proc. VLSI-DAT, 2010, pp. 335--338."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_13_1","DOI":"10.1145\/240518.240595"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_14_1","DOI":"10.1109\/TCAD.2008.925776"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_15_1","DOI":"10.1109\/TCAD.2008.2006155"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_16_1","DOI":"10.1109\/TCAD.2011.2106852"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_17_1","DOI":"10.1145\/2160916.2160943"},{"key":"e_1_3_2_1_18_1","volume-title":"Electrical and Computer Engineering","author":"Tsai J.-L.","year":"2005","unstructured":"J.-L. Tsai , \"Clock Tree Synthesis for Timing Convergence and Timing Yield Improvement in Nanometer Technologies\", Ph. D. Thesis , Electrical and Computer Engineering , University of Wisconsin-Madison , 2005 . J.-L. Tsai, \"Clock Tree Synthesis for Timing Convergence and Timing Yield Improvement in Nanometer Technologies\", Ph.D. Thesis, Electrical and Computer Engineering, University of Wisconsin-Madison, 2005."},{"key":"e_1_3_2_1_19_1","first-page":"336","volume-title":"Proc. ICCAD","author":"Tsay R.-S.","year":"1991","unstructured":"R.-S. Tsay , \"Exact Zero-Skew\" , Proc. ICCAD , 1991 , pp. 336 -- 339 . R.-S. Tsay, \"Exact Zero-Skew\", Proc. ICCAD, 1991, pp. 336--339."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_20_1","DOI":"10.5555\/789083.1022707"},{"key":"e_1_3_2_1_21_1","volume-title":"November","author":"Broadcom Corporation (networking infrastructure physical design principal engineer)","year":"2013","unstructured":"Broadcom Corporation (networking infrastructure physical design principal engineer) , personal communication , November 2013 . Broadcom Corporation (networking infrastructure physical design principal engineer), personal communication, November 2013."},{"key":"e_1_3_2_1_22_1","volume-title":"November","author":"Samsung Electronics Corporation (System LSI application processor principal engineer)","year":"2013","unstructured":"Samsung Electronics Corporation (System LSI application processor principal engineer) , personal communication , November 2013 . Samsung Electronics Corporation (System LSI application processor principal engineer), personal communication, November 2013."},{"unstructured":"ISPD CNS Contest. http:\/\/ispd.cc\/contests\/09\/ispd09cts.html  ISPD CNS Contest. http:\/\/ispd.cc\/contests\/09\/ispd09cts.html","key":"e_1_3_2_1_23_1"},{"unstructured":"OpenCores. http:\/\/opencores.org  OpenCores. http:\/\/opencores.org","key":"e_1_3_2_1_24_1"},{"unstructured":"Synopsys PrimeTime User's Manual. http:\/\/www.synopsys.com\/Tools\/Implementation\/Signoff\/PrimeTime\/Pages\/  Synopsys PrimeTime User's Manual. http:\/\/www.synopsys.com\/Tools\/Implementation\/Signoff\/PrimeTime\/Pages\/","key":"e_1_3_2_1_25_1"},{"unstructured":"UC Benchmark Suite for Gate Sizing. http:\/\/vlsicad.ucsd.edu\/SIZING\/bench\/artificial.html  UC Benchmark Suite for Gate Sizing. http:\/\/vlsicad.ucsd.edu\/SIZING\/bench\/artificial.html","key":"e_1_3_2_1_26_1"}],"event":{"sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA","IEEE CASS"],"acronym":"GLSVLSI '14","name":"GLSVLSI '14: Great Lakes Symposium on VLSI 2014","location":"Houston Texas USA"},"container-title":["Proceedings of the 24th edition of the great lakes symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2591513.2591541","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2591513.2591541","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T06:55:59Z","timestamp":1750229759000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2591513.2591541"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,5,20]]},"references-count":26,"alternative-id":["10.1145\/2591513.2591541","10.1145\/2591513"],"URL":"https:\/\/doi.org\/10.1145\/2591513.2591541","relation":{},"subject":[],"published":{"date-parts":[[2014,5,20]]},"assertion":[{"value":"2014-05-20","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}