{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:17:21Z","timestamp":1750306641285,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":13,"publisher":"ACM","license":[{"start":{"date-parts":[[2014,5,20]],"date-time":"2014-05-20T00:00:00Z","timestamp":1400544000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2014,5,20]]},"DOI":"10.1145\/2591513.2591590","type":"proceedings-article","created":{"date-parts":[[2014,5,27]],"date-time":"2014-05-27T12:57:10Z","timestamp":1401195430000},"page":"45-50","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["High level energy modeling of controller logic in data caches"],"prefix":"10.1145","author":[{"given":"Preeti Ranjan","family":"Panda","sequence":"first","affiliation":[{"name":"Indian Institute of Technology Delhi, NEW DELHI, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sourav","family":"Roy","sequence":"additional","affiliation":[{"name":"Freescale Semiconductor India Pvt. Ltd., Noida, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Srikanth","family":"Chandrasekaran","sequence":"additional","affiliation":[{"name":"Freescale Semiconductor India Pvt. Ltd., Noida, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Namita","family":"Sharma","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Delhi, NEW DELHI, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jasleen","family":"Kaur","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Delhi, NEW DELHI, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sarath Kumar","family":"Kandalam","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Delhi, NEW DELHI, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nagaraj","family":"N.","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Delhi, NEW DELHI, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2014,5,20]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/263272.263310"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.2"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2091686"},{"key":"e_1_3_2_1_5_1","volume-title":"CA","author":"Handy J.","year":"1993","unstructured":"J. Handy , phThe cache memory book.\\hskip 1em plus 0.5em minus 0.4em\\relax San Diego , CA , USA : Academic Press Professional , Inc., 1993 . J. Handy, phThe cache memory book.\\hskip 1em plus 0.5em minus 0.4em\\relax San Diego, CA, USA: Academic Press Professional, Inc., 1993."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/ECBS.2006.52"},{"key":"e_1_3_2_1_7_1","unstructured":"\"Ultra Low-Power Intel\u00ae Embedded Processor.\" http:\/\/www.intel.com\/design\/intarch\/prodbref\/272713.htm  \"Ultra Low-Power Intel\u00ae Embedded Processor.\" http:\/\/www.intel.com\/design\/intarch\/prodbref\/272713.htm"},{"key":"e_1_3_2_1_8_1","unstructured":"\\BIBentryALTinterwordspacing\"Powerpc g4 architecture white paper.\" http:\/\/cache.freescale.com\/files\/product\/doc\/G4WP.pdf\\BIBentrySTDinterwordspacing  \\BIBentryALTinterwordspacing\"Powerpc g4 architecture white paper.\" http:\/\/cache.freescale.com\/files\/product\/doc\/G4WP.pdf\\BIBentrySTDinterwordspacing"},{"key":"e_1_3_2_1_9_1","unstructured":"http:www.caviumnetworks.com  http:www.caviumnetworks.com"},{"volume-title":"Design Issues and Tradeoffs for Write Buffers,\" HPCA 1997","author":"Skadron K.","key":"e_1_3_2_1_10_1","unstructured":"K. Skadron and D. W. Clark , \" Design Issues and Tradeoffs for Write Buffers,\" HPCA 1997 K. Skadron and D. W. Clark, \"Design Issues and Tradeoffs for Write Buffers,\" HPCA 1997"},{"volume-title":"Rep. EC-QAEQD-TE","year":"1996","key":"e_1_3_2_1_11_1","unstructured":"DEC, \"Alpha 21164 microprocessor , hardware reference manual,\"Tech . Rep. EC-QAEQD-TE , 1996 . DEC, \"Alpha 21164 microprocessor, hardware reference manual,\"Tech. Rep. EC-QAEQD-TE, 1996."},{"key":"e_1_3_2_1_12_1","volume-title":"phComputer Architecture - A Quantitative Approach.\\hskip 1em plus 0.5em minus 0.4em\\relax Elsevier","author":"Hennessy J. L.","year":"1990","unstructured":"J. L. Hennessy and D. A. Patterson , phComputer Architecture - A Quantitative Approach.\\hskip 1em plus 0.5em minus 0.4em\\relax Elsevier , 1990 . J. L. Hennessy and D. A. Patterson, phComputer Architecture - A Quantitative Approach.\\hskip 1em plus 0.5em minus 0.4em\\relax Elsevier, 1990."},{"key":"e_1_3_2_1_13_1","unstructured":"\\BIBentryALTinterwordspacing\"The SimpleScalar Architectural Research Tool version 3.0.\"http:\/\/www.simplescalar.com\/\\BIBentrySTDinterwordspacing  \\BIBentryALTinterwordspacing\"The SimpleScalar Architectural Research Tool version 3.0.\"http:\/\/www.simplescalar.com\/\\BIBentrySTDinterwordspacing"},{"key":"e_1_3_2_1_14_1","volume-title":"NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory.\" TCAD, 31(7)","author":"Dong X.","year":"2012","unstructured":"X. Dong ,\" NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory.\" TCAD, 31(7) , 2012 . X. Dong et al.,\"NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory.\" TCAD, 31(7), 2012."}],"event":{"name":"GLSVLSI '14: Great Lakes Symposium on VLSI 2014","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA","IEEE CASS"],"location":"Houston Texas USA","acronym":"GLSVLSI '14"},"container-title":["Proceedings of the 24th edition of the great lakes symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2591513.2591590","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2591513.2591590","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T06:55:59Z","timestamp":1750229759000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2591513.2591590"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,5,20]]},"references-count":13,"alternative-id":["10.1145\/2591513.2591590","10.1145\/2591513"],"URL":"https:\/\/doi.org\/10.1145\/2591513.2591590","relation":{},"subject":[],"published":{"date-parts":[[2014,5,20]]},"assertion":[{"value":"2014-05-20","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}