{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,2]],"date-time":"2026-07-02T23:41:18Z","timestamp":1783035678205,"version":"3.54.6"},"publisher-location":"New York, NY, USA","reference-count":21,"publisher":"ACM","license":[{"start":{"date-parts":[[2014,6,16]],"date-time":"2014-06-16T00:00:00Z","timestamp":1402876800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100004963","name":"Seventh Framework Programme","doi-asserted-by":"publisher","award":["318693"],"award-info":[{"award-number":["318693"]}],"id":[{"id":"10.13039\/501100004963","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000143","name":"Division of Computing and Communication Foundations","doi-asserted-by":"publisher","award":["CCF12122962"],"award-info":[{"award-number":["CCF12122962"]}],"id":[{"id":"10.13039\/100000143","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Ministry of Science and Technology of Spain and the European Union (FEDER funds)","award":["TIN2008-02055-E, TIN2012-34557"],"award-info":[{"award-number":["TIN2008-02055-E, TIN2012-34557"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2014,6,16]]},"DOI":"10.1145\/2591971.2591994","type":"proceedings-article","created":{"date-parts":[[2014,6,10]],"date-time":"2014-06-10T08:50:25Z","timestamp":1402390225000},"page":"491-504","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":42,"title":["Neighbor-cell assisted error correction for MLC NAND flash memories"],"prefix":"10.1145","author":[{"given":"Yu","family":"Cai","sequence":"first","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh, PA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Gulay","family":"Yalcin","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh, PA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Erich F.","family":"Haratsch","sequence":"additional","affiliation":[{"name":"LSI Corporation, San Jose, CA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Osman","family":"Unsal","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Adrian","family":"Cristal","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ken","family":"Mai","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh, PA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2014,6,16]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"DATE","author":"Cai Y.","year":"2012","unstructured":"Y. Cai MLC NAND Flash Memory : Measurement, Characterization and Analysis \", DATE 2012 . Y. Cai et al., \"Error Patterns in MLC NAND Flash Memory: Measurement, Characterization and Analysis\", DATE 2012."},{"key":"e_1_3_2_1_2_1","volume-title":"IRPS","author":"Mielke N.","year":"2008","unstructured":"N. Mielke , \"Bit Error Rate in NAND Flash Memories\" , IRPS 2008 . N. Mielke, \"Bit Error Rate in NAND Flash Memories\", IRPS 2008."},{"key":"e_1_3_2_1_3_1","volume-title":"ICCD","author":"Cai Y.","year":"2013","unstructured":"Y. Cai MLC NAND Flash Memory : Characterization, Modeling, and Mitigation \", ICCD 2013 . Y. Cai et al., \"Program Interference in MLC NAND Flash Memory: Characterization, Modeling, and Mitigation\", ICCD 2013."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/2485288.2485597"},{"key":"e_1_3_2_1_5_1","volume-title":"JSSC","author":"Park K.","year":"2008","unstructured":"K. Park A Zeroing Cell-to-cell Interference Page Architecture with Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories\" , JSSC 2008 . K. Park et al., \"A Zeroing Cell-to-cell Interference Page Architecture with Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories\", JSSC 2008."},{"key":"e_1_3_2_1_6_1","volume-title":"FAST","author":"Liu R.","year":"2012","unstructured":"R. Liu NAND Flash-Based SSDs via Retention Relaxation\" , FAST 2012 . R. Liu et al., \"Optimizing NAND Flash-Based SSDs via Retention Relaxation\", FAST 2012."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2012.6378623"},{"key":"e_1_3_2_1_8_1","article-title":"Error Analysis and Retention-Aware Error Management for NAND flash memory","author":"Cai Y.","year":"2013","unstructured":"Y. Cai , \" Error Analysis and Retention-Aware Error Management for NAND flash memory ,\" Intel Technology Journal 2013 . Y. Cai et al., \"Error Analysis and Retention-Aware Error Management for NAND flash memory,\" Intel Technology Journal 2013.","journal-title":"Intel Technology Journal"},{"key":"e_1_3_2_1_9_1","volume-title":"VLSIT","author":"Shim H.","year":"2011","unstructured":"H. Shim , \" Highly Reliable 26nm 64Gb MLC E2NAND Flash Memory with MSP Controller \", VLSIT , 2011 . H. Shim et al., \"Highly Reliable 26nm 64Gb MLC E2NAND Flash Memory with MSP Controller\", VLSIT, 2011."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2013.2251417"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2046966"},{"key":"e_1_3_2_1_12_1","volume-title":"Error Control Coding","author":"Lin S.","year":"2004","unstructured":"S. Lin , \" Error Control Coding ( 2 nd Edition)\", Prentice Hall 2004 . S. Lin et al., \"Error Control Coding (2nd Edition)\", Prentice Hall 2004.","edition":"2"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2011.28"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.4218\/etrij.13.0212.0273"},{"key":"e_1_3_2_1_15_1","volume-title":"JSSC","author":"Kim C.","year":"2012","unstructured":"C. Kim A 21 nm High Performance 64 Gb MLC NAND Flash Memory with 40 0 MB\/s Asynchronous Toggle DDR Interface\" , JSSC 2012 . C. Kim et al., \"A 21 nm High Performance 64 Gb MLC NAND Flash Memory with 400 MB\/s Asynchronous Toggle DDR Interface\", JSSC 2012."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TSP.2012.2222399"},{"key":"e_1_3_2_1_17_1","volume-title":"FMS","author":"Yasarapu S.","year":"2011","unstructured":"S. Yasarapu , \"Architectural Requirements for MLC based SSDs\" , FMS 2011 . S. Yasarapu, \"Architectural Requirements for MLC based SSDs\", FMS 2011."},{"key":"e_1_3_2_1_19_1","volume-title":"USENIX","author":"Agrawal N.","year":"2008","unstructured":"N. Agrawal SSD Performance\" , USENIX 2008 . N. Agrawal et al., \"Design Tradeoffs for SSD Performance\", USENIX 2008."},{"key":"e_1_3_2_1_20_1","unstructured":"Open Source at HP Labs http:\/\/tesla.hpl.hp.com\/opensource  Open Source at HP Labs http:\/\/tesla.hpl.hp.com\/opensource"},{"key":"e_1_3_2_1_22_1","unstructured":"SNIA\n  : IOTTA Repository http:\/\/iotta.snia.org\/tracetypes\/3.  SNIA: IOTTA Repository http:\/\/iotta.snia.org\/tracetypes\/3."},{"key":"e_1_3_2_1_23_1","unstructured":"UMass Trace: http:\/\/traces.cs.umass.edu\/index.php\/Storage\/Storage  UMass Trace: http:\/\/traces.cs.umass.edu\/index.php\/Storage\/Storage"}],"event":{"name":"SIGMETRICS '14: ACM SIGMETRICS \/ International Conference on Measurement and Modeling of Computer Systems","location":"Austin Texas USA","acronym":"SIGMETRICS '14","sponsor":["SIGMETRICS ACM Special Interest Group on Measurement and Evaluation"]},"container-title":["The 2014 ACM international conference on Measurement and modeling of computer systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2591971.2591994","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2591971.2591994","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:55:57Z","timestamp":1750215357000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2591971.2591994"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,6,16]]},"references-count":21,"alternative-id":["10.1145\/2591971.2591994","10.1145\/2591971"],"URL":"https:\/\/doi.org\/10.1145\/2591971.2591994","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/2637364.2591994","asserted-by":"object"}]},"subject":[],"published":{"date-parts":[[2014,6,16]]},"assertion":[{"value":"2014-06-16","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}