{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:18:07Z","timestamp":1750306687122,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":9,"publisher":"ACM","license":[{"start":{"date-parts":[[2014,6,1]],"date-time":"2014-06-01T00:00:00Z","timestamp":1401580800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2014,6]]},"DOI":"10.1145\/2593069.2593167","type":"proceedings-article","created":{"date-parts":[[2014,5,27]],"date-time":"2014-05-27T12:57:10Z","timestamp":1401195430000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":26,"title":["On Enhancing Power Benefits in 3D ICs"],"prefix":"10.1145","author":[{"given":"Moongon","family":"Jung","sequence":"first","affiliation":[{"name":"School of ECE, Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Taigon","family":"Song","sequence":"additional","affiliation":[{"name":"School of ECE, Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yang","family":"Wan","sequence":"additional","affiliation":[{"name":"School of ECE, Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yarui","family":"Peng","sequence":"additional","affiliation":[{"name":"School of ECE, Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sung Kyu","family":"Lim","sequence":"additional","affiliation":[{"name":"School of ECE, Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2014,6]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.18"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2034408"},{"key":"e_1_3_2_1_3_1","volume-title":"Power-Efficient SPARC SoC. In IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers","author":"Nawathe U.","year":"2007","unstructured":"U. Nawathe Power-Efficient SPARC SoC. In IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers , 2007 . U. Nawathe et al. An 8-Core 64-Thread 64b Power-Efficient SPARC SoC. In IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2007."},{"key":"e_1_3_2_1_4_1","author":"Katti G.","year":"2010","unstructured":"G. Katti Cs. In IEEE Trans. on Electron Devices , 2010 . G. Katti et al. Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs. In IEEE Trans. on Electron Devices, 2010.","journal-title":"Trans. on Electron Devices"},{"key":"e_1_3_2_1_5_1","volume-title":"IC Design with Through-Silicon-Via Planning. In Proc. Asia and South Pacific Design Automation Conf.","author":"Kim D.","year":"2012","unstructured":"D. Kim IC Design with Through-Silicon-Via Planning. In Proc. Asia and South Pacific Design Automation Conf. , 2012 . D. Kim et al. Block-level 3D IC Design with Through-Silicon-Via Planning. In Proc. Asia and South Pacific Design Automation Conf., 2012."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687524"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.925783"},{"key":"e_1_3_2_1_8_1","author":"Luo G.","year":"2013","unstructured":"G. Luo D I Cs and Its Extension on Thermal Awareness. In IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems , 2013 . G. Luo et al. An Analytical Placement Framework for 3-D ICs and Its Extension on Thermal Awareness. In IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 2013.","journal-title":"Trans. on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"e_1_3_2_1_9_1","author":"Hsu M.","year":"2013","unstructured":"M. Hsu D IC Designs Based on a Novel Weighted-Average Wirelength Model. In IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems , 2013 . M. Hsu et al. TSV-Aware Analytical Placement for 3-D IC Designs Based on a Novel Weighted-Average Wirelength Model. In IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 2013.","journal-title":"Trans. on Computer-Aided Design of Integrated Circuits and Systems"}],"event":{"name":"DAC '14: The 51st Annual Design Automation Conference 2014","sponsor":["EDAC Electronic Design Automation Consortium","SIGBED ACM Special Interest Group on Embedded Systems","SIGDA ACM Special Interest Group on Design Automation","IEEE-CEDA"],"location":"San Francisco CA USA","acronym":"DAC '14"},"container-title":["Proceedings of the 51st Annual Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2593069.2593167","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2593069.2593167","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T07:01:24Z","timestamp":1750230084000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2593069.2593167"}},"subtitle":["Block Folding and Bonding Styles Perspective"],"short-title":[],"issued":{"date-parts":[[2014,6]]},"references-count":9,"alternative-id":["10.1145\/2593069.2593167","10.1145\/2593069"],"URL":"https:\/\/doi.org\/10.1145\/2593069.2593167","relation":{},"subject":[],"published":{"date-parts":[[2014,6]]},"assertion":[{"value":"2014-06-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}