{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,15]],"date-time":"2026-03-15T09:47:40Z","timestamp":1773568060268,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":18,"publisher":"ACM","license":[{"start":{"date-parts":[[2014,6,1]],"date-time":"2014-06-01T00:00:00Z","timestamp":1401580800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2014,6]]},"DOI":"10.1145\/2593069.2593227","type":"proceedings-article","created":{"date-parts":[[2014,5,27]],"date-time":"2014-05-27T12:57:10Z","timestamp":1401195430000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["TACUE"],"prefix":"10.1145","author":[{"given":"Mahmoud","family":"Elbayoumi","sequence":"first","affiliation":[{"name":"ECE Dept., Virginia Tech, Blacksburg, VA, USA, 24061"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mihir","family":"Choudhury","sequence":"additional","affiliation":[{"name":"IBM T. J. Watson Research Center, Yorktown Heights, NY, USA, 10598"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Victor","family":"Kravets","sequence":"additional","affiliation":[{"name":"IBM T. J. Watson Research Center, Yorktown Heights, NY, USA, 10598"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andrew","family":"Sullivan","sequence":"additional","affiliation":[{"name":"IBM T. J. Watson Research Center, Yorktown Heights, NY, USA, 10598"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael","family":"Hsiao","sequence":"additional","affiliation":[{"name":"ECE Dept., Virginia Tech, Blacksburg, VA, USA, 24061"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mustafa","family":"Elnainay","sequence":"additional","affiliation":[{"name":"Computer and Systems Engineering Department, Alexandria University, Alexandria, Egypt, 21544"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2014,6]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Power and delay aware synthesis of multi-operand adders targeting lut-based fpgas. sym. on Low-power elect. and des","author":"T.","year":"2011","unstructured":"T. Matsunaga et. al. Power and delay aware synthesis of multi-operand adders targeting lut-based fpgas. sym. on Low-power elect. and des ., 2011 . T. Matsunaga et. al. Power and delay aware synthesis of multi-operand adders targeting lut-based fpgas. sym. on Low-power elect. and des., 2011."},{"key":"e_1_3_2_1_2_1","volume-title":"Power\/area\/delay aware fsm synthesis and optimization","author":"Shiue W.","year":"2005","unstructured":"W. Shiue . Power\/area\/delay aware fsm synthesis and optimization . Elsevier Mic . J., 2005 . W. Shiue. Power\/area\/delay aware fsm synthesis and optimization. Elsevier Mic. J., 2005."},{"key":"e_1_3_2_1_3_1","volume-title":"ICEE","author":"V.","year":"2013","unstructured":"V. Sklyarov et. al. Synthesis of parallel hierarchical finite state machines . ICEE , 2013 . V. Sklyarov et. al. Synthesis of parallel hierarchical finite state machines. ICEE, 2013."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488793"},{"key":"e_1_3_2_1_5_1","volume-title":"Performance enhancement through optimization in fpga synthesis: Constraint specific approach","author":"R.","year":"2013","unstructured":"R. Uma et. al. Performance enhancement through optimization in fpga synthesis: Constraint specific approach . 2013 . R. Uma et. al. Performance enhancement through optimization in fpga synthesis: Constraint specific approach. 2013."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488792"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1127908.1127927"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233531"},{"key":"e_1_3_2_1_9_1","volume-title":"DATE","author":"O.","year":"2010","unstructured":"O. Martinello Jr et. al. Kl-cuts : a new approach for logic synthesis targeting multiple output blocks . DATE , 2010 . O. Martinello Jr et. al. Kl-cuts: a new approach for logic synthesis targeting multiple output blocks. DATE, 2010."},{"key":"e_1_3_2_1_10_1","volume-title":"Finding all convex cuts of a plane graph in cubic time","author":"R.","year":"2013","unstructured":"R. Glantz et. al. Finding all convex cuts of a plane graph in cubic time . Springer , Alg . and Comp., 2013 . R. Glantz et. al. Finding all convex cuts of a plane graph in cubic time. Springer, Alg. and Comp., 2013."},{"key":"e_1_3_2_1_11_1","volume-title":"B.","author":"E.","year":"1992","unstructured":"E. Sentovich et. al. Sis: A system for sequential circuit synthesis. U. C ., B. , 1992 . E. Sentovich et. al. Sis: A system for sequential circuit synthesis. U. C., B., 1992."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.404.0407"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14295-6_5"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.1013899"},{"key":"e_1_3_2_1_15_1","volume-title":"ICCAD","author":"M.","year":"2010","unstructured":"M. Choudhury et. al. Bi-decomposition of large boolean functions using blocking edge graphs . ICCAD , 2010 . M. Choudhury et. al. Bi-decomposition of large boolean functions using blocking edge graphs. ICCAD, 2010."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.811447"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/774572.774673"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1137\/0203006"}],"event":{"name":"DAC '14: The 51st Annual Design Automation Conference 2014","location":"San Francisco CA USA","acronym":"DAC '14","sponsor":["EDAC Electronic Design Automation Consortium","SIGBED ACM Special Interest Group on Embedded Systems","SIGDA ACM Special Interest Group on Design Automation","IEEE-CEDA"]},"container-title":["Proceedings of the 51st Annual Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2593069.2593227","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2593069.2593227","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T07:01:11Z","timestamp":1750230071000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2593069.2593227"}},"subtitle":["A Timing-Aware Cuts Enumeration Algorithm for Parallel Synthesis"],"short-title":[],"issued":{"date-parts":[[2014,6]]},"references-count":18,"alternative-id":["10.1145\/2593069.2593227","10.1145\/2593069"],"URL":"https:\/\/doi.org\/10.1145\/2593069.2593227","relation":{},"subject":[],"published":{"date-parts":[[2014,6]]},"assertion":[{"value":"2014-06-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}