{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,14]],"date-time":"2026-03-14T17:57:57Z","timestamp":1773511077804,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":39,"publisher":"ACM","license":[{"start":{"date-parts":[[2014,6,10]],"date-time":"2014-06-10T00:00:00Z","timestamp":1402358400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2014,6,10]]},"DOI":"10.1145\/2597652.2597655","type":"proceedings-article","created":{"date-parts":[[2014,6,10]],"date-time":"2014-06-10T12:50:25Z","timestamp":1402404625000},"page":"53-62","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":51,"title":["Last-level cache deduplication"],"prefix":"10.1145","author":[{"given":"Yingying","family":"Tian","sequence":"first","affiliation":[{"name":"Texas A&M University, College Station, TX, USA"}]},{"given":"Samira M.","family":"Khan","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University, Intel Labs, Pittsburgh, PA, USA"}]},{"given":"Daniel A.","family":"Jim\u00e9nez","sequence":"additional","affiliation":[{"name":"Texas A&M University, College Station, TX, USA"}]},{"given":"Gabriel H.","family":"Loh","sequence":"additional","affiliation":[{"name":"Advanced Micro Devices, Inc., Sunnyvale, CA, USA"}]}],"member":"320","published-online":{"date-parts":[[2014,6,10]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.5555\/998680.1006719"},{"key":"e_1_3_2_1_2_1","volume-title":"Frequent pattern compression: A significance-based compression schemefor l2 caches. Dept. of Computer Sciences","author":"Alameldeen A.R.","year":"2004","unstructured":"A.R. Alameldeen and D.A. Wood . Frequent pattern compression: A significance-based compression schemefor l2 caches. Dept. of Computer Sciences , University of Wisconsin-Madison , Tech. Rep, 2004 . A.R. Alameldeen and D.A. Wood. Frequent pattern compression: A significance-based compression schemefor l2 caches. Dept. of Computer Sciences, University of Wisconsin-Madison, Tech. Rep, 2004."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555777"},{"key":"e_1_3_2_1_4_1","volume-title":"Proceedings of the Singapore-MIT Alliance Symposium","author":"Chen D.","year":"2003","unstructured":"D. Chen , E. Peserico , and L. Rudolph . A dynamically partitionable compressed cache . In Proceedings of the Singapore-MIT Alliance Symposium , January 2003 . D. Chen, E. Peserico, and L. Rudolph. A dynamically partitionable compressed cache. In Proceedings of the Singapore-MIT Alliance Symposium, January 2003."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2151007"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2086696.2086714"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1542275.1542288"},{"key":"e_1_3_2_1_9_1","volume-title":"April 4th","author":"Green R. W.","year":"2013","unstructured":"R. W. Green . Memory movement and initialization: Optimization and control. http:\/\/software.intel.com\/ , April 4th , 2013 . R. W. Green. Memory movement and initialization: Optimization and control. http:\/\/software.intel.com\/, April 4th, 2013."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.4"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"e_1_3_2_1_12_1","volume-title":"Proceedings of the 21st Symposium on Mass Storage Systems (MSS'04)","author":"Hong B.","year":"2004","unstructured":"B. Hong , D. Plantenberg , D.D.E. Long , and M. Sivan-Zimet . Duplicate data elimination in a sanfile system . In Proceedings of the 21st Symposium on Mass Storage Systems (MSS'04) , Goddard, MD , 2004 . B. Hong, D. Plantenberg, D.D.E. Long, and M. Sivan-Zimet. Duplicate data elimination in a sanfile system. In Proceedings of the 21st Symposium on Mass Storage Systems (MSS'04), Goddard, MD, 2004."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.52"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2189750.2151003"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.24"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403720"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.5555\/2015976.2015983"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5434033"},{"key":"e_1_3_2_1_19_1","first-page":"184","volume-title":"Computer Design, 1999.(ICCD'99) International Conference on","author":"Lee J.S.","year":"1999","unstructured":"J.S. Lee , W.K. Hong , and S.D. Kim . Design and evaluation of a selective compressed memory system . In Computer Design, 1999.(ICCD'99) International Conference on , pages 184 -- 191 . IEEE, 1999 . J.S. Lee, W.K. Hong, and S.D. Kim. Design and evaluation of a selective compressed memory system. In Computer Design, 1999.(ICCD'99) International Conference on, pages 184--191. IEEE, 1999."},{"key":"e_1_3_2_1_20_1","volume-title":"International journal of computers & applications, 25(2):98--105","author":"Lee J.S.","year":"2003","unstructured":"J.S. Lee , W.K. Hong , and S.D. Kim . Adaptive methods to minimize decompression overhead for compressed on-chip caches . International journal of computers & applications, 25(2):98--105 , 2003 . J.S. Lee, W.K. Hong, and S.D. Kim. Adaptive methods to minimize decompression overhead for compressed on-chip caches. International journal of computers & applications, 25(2):98--105, 2003."},{"key":"e_1_3_2_1_21_1","volume-title":"Intel Performance Analysis Guide","author":"Levinthal D.","year":"2009","unstructured":"D. Levinthal . Performance analysis guide for intel core i7 processor and intel xeon 5500 processors . Intel Performance Analysis Guide , 2009 . D. Levinthal. Performance analysis guide for intel core i7 processor and intel xeon 5500 processors. Intel Performance Analysis Guide, 2009."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/871506.871574"},{"key":"e_1_3_2_1_23_1","volume-title":"Proceedings of 23rd IEEE Conference on Mass Storage Systems and Technologies","author":"Grunwald C.B.","year":"2006","unstructured":"C.B. Morrey III and D. Grunwald . Content-based block caching . In Proceedings of 23rd IEEE Conference on Mass Storage Systems and Technologies , College Park, Maryland , May 2006 . C.B. Morrey III and D. Grunwald. Content-based block caching. In Proceedings of 23rd IEEE Conference on Mass Storage Systems and Technologies, College Park, Maryland, May 2006."},{"key":"e_1_3_2_1_24_1","volume-title":"HP Laboratories","author":"Muralimanohar N.","year":"2009","unstructured":"N. Muralimanohar , R. Balasubramonian , and N.P. Jouppi . Cacti 6.0: A tool to model large caches. Research report hpl-2009-85 , HP Laboratories , 2009 . N. Muralimanohar, R. Balasubramonian, and N.P. Jouppi. Cacti 6.0: A tool to model large caches. Research report hpl-2009-85, HP Laboratories, 2009."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.jalgor.2003.12.002"},{"key":"e_1_3_2_1_26_1","first-page":"29","volume-title":"1st International Qemu Users' Forum","author":"Patel A.","year":"2011","unstructured":"A. Patel , F. Afram , and K. Ghose . Marss-x86: A qemu-based micro-architectural and systems simulator for x86 multicore processors . In 1st International Qemu Users' Forum , pages 29 -- 30 , 2011 . A. Patel, F. Afram, and K. Ghose. Marss-x86: A qemu-based micro-architectural and systems simulator for x86 multicore processors. In 1st International Qemu Users' Forum, pages 29--30, 2011."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540724"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370870"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/781027.781076"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.52"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.20"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.5555\/1115694.1115812"},{"key":"e_1_3_2_1_33_1","first-page":"1","volume-title":"Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on","author":"Seongil O.","year":"2011","unstructured":"O. Seongil , S. Choo , and J.H. Ahn . Exploring energy-efficient dram array organizations . In Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on , pages 1 -- 4 . IEEE, 2011 . O. Seongil, S. Choo, and J.H. Ahn. Exploring energy-efficient dram array organizations. In Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on, pages 1--4. IEEE, 2011."},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/173682.165152"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.13"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/360128.360150"},{"issue":"1","key":"e_1_3_2_1_37_1","first-page":"145","article-title":"Power7, a highly parallel, scalable multi-core high end server processor. Solid-State Circuits","volume":"46","author":"Wendel D.F.","year":"2011","unstructured":"D.F. Wendel , R. Kalla , J. Warnock , R. Cargnoni , S.G. Chu , J.G. Clabes , D. Dreps , D. Hrusecky , J. Friedrich , S. Islam , Power7, a highly parallel, scalable multi-core high end server processor. Solid-State Circuits , IEEE Journal of , 46 ( 1 ): 145 -- 161 , 2011 . D.F. Wendel, R. Kalla, J. Warnock, R. Cargnoni, S.G. Chu, J.G. Clabes, D. Dreps, D. Hrusecky, J. Friedrich, S. Islam, et al. Power7, a highly parallel, scalable multi-core high end server processor. Solid-State Circuits, IEEE Journal of, 46(1):145--161, 2011.","journal-title":"IEEE Journal of"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/360128.360154"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2010.5470468"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/384264.379235"}],"event":{"name":"ICS'14: 2014 International Conference on Supercomputing","location":"Munich Germany","acronym":"ICS'14","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture"]},"container-title":["Proceedings of the 28th ACM international conference on Supercomputing"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2597652.2597655","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2597652.2597655","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:09:58Z","timestamp":1750234198000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2597652.2597655"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,6,10]]},"references-count":39,"alternative-id":["10.1145\/2597652.2597655","10.1145\/2597652"],"URL":"https:\/\/doi.org\/10.1145\/2597652.2597655","relation":{},"subject":[],"published":{"date-parts":[[2014,6,10]]},"assertion":[{"value":"2014-06-10","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}