{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:17:29Z","timestamp":1763468249173,"version":"3.41.0"},"reference-count":26,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2014,12,29]],"date-time":"2014-12-29T00:00:00Z","timestamp":1419811200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000143","name":"Division of Computing and Communication Foundations","doi-asserted-by":"publisher","award":["CCF-0904577"],"award-info":[{"award-number":["CCF-0904577"]}],"id":[{"id":"10.13039\/100000143","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2015,1,23]]},"abstract":"<jats:p>\n            Timing Extraction identifies the delay of fine-grained components within an FPGA. From these computed delays, the delay of any path can be calculated. Moreover, a comparison of the fine-grained delays allows a detailed understanding of the amount and type of process variation that exists in the FPGA. To obtain these delays, Timing Extraction measures, using only resources already available in the FPGA, the delay of a small subset of the total paths in the FPGA. We apply Timing Extraction to the Logic Array Block (LAB) on an Altera Cyclone III FPGA to obtain a view of the delay down to near-individual LUT SRAM cell granularity, characterizing components with delays on the order of tens to a few hundred picoseconds with a resolution of \u00b13.2ps, matching the expected error bounds. This information reveals that the 65nm process used has, on average, random variation of \u03c3 \u03bc =4.0% with components having an average maximum spread of 83ps. Timing Extraction also shows that as V\n            <jats:sub>\n              <jats:italic>DD<\/jats:italic>\n            <\/jats:sub>\n            decreases from 1.2V to 0.9V in a Cyclone IV 60nm FPGA, paths slow down, and variation increases from \u03c3 \u03bc =4.3% to \u03c3 \u03bc =5.8%, a clear indication that lowering V\n            <jats:sub>\n              <jats:italic>DD<\/jats:italic>\n            <\/jats:sub>\n            magnifies the impact of random variation.\n          <\/jats:p>","DOI":"10.1145\/2597889","type":"journal-article","created":{"date-parts":[[2015,1,5]],"date-time":"2015-01-05T13:27:09Z","timestamp":1420464429000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":16,"title":["GROK-LAB"],"prefix":"10.1145","volume":"7","author":[{"given":"Benjamin","family":"Gojman","sequence":"first","affiliation":[{"name":"University of Pennsylvania, Philadelphia, PA"}]},{"given":"Sirisha","family":"Nalmela","sequence":"additional","affiliation":[{"name":"Juniper Networks, Westford, MA"}]},{"given":"Nikil","family":"Mehta","sequence":"additional","affiliation":[{"name":"California Institute of Technology, Pasadena, CA"}]},{"given":"Nicholas","family":"Howarth","sequence":"additional","affiliation":[{"name":"University of Pennsylvania, Philadelphia, PA"}]},{"given":"Andr\u00e9","family":"Dehon","sequence":"additional","affiliation":[{"name":"University of Pennsylvania, Philadelphia, PA"}]}],"member":"320","published-online":{"date-parts":[[2014,12,29]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"Altera. 2003. DE0-Nano Development and Education Board. http:\/\/www.altera.com\/education\/univ\/materials\/boards\/de0-nano\/unv-de0-nano-board.html.  Altera. 2003. DE0-Nano Development and Education Board. http:\/\/www.altera.com\/education\/univ\/materials\/boards\/de0-nano\/unv-de0-nano-board.html."},{"key":"e_1_2_1_2_1","unstructured":"Altera. 2005a. QUIP. http:\/\/www.altera.com\/education\/univ\/research\/quip\/unv-quip.html. (2005).  Altera. 2005a. QUIP. http:\/\/www.altera.com\/education\/univ\/research\/quip\/unv-quip.html. (2005)."},{"volume-title":"LCELL WYSIWYG Description for Cyclone II","key":"e_1_2_1_3_1","unstructured":"Altera. 2005b. LCELL WYSIWYG Description for Cyclone II , Altera Corporation . Altera. 2005b. LCELL WYSIWYG Description for Cyclone II, Altera Corporation."},{"volume-title":"LCELL WYSIWYG Description for Cyclone III","key":"e_1_2_1_4_1","unstructured":"Altera. 2009. LCELL WYSIWYG Description for Cyclone III , Altera Corporation . Altera. 2009. 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Dynamic voltage scaling for commercial FPGAs. In Proceedings of the International Conference on Field-Programmable Technology (December 2005), 173--180."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.5555\/549928.795751"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.645062"},{"key":"e_1_2_1_9_1","first-page":"381","article-title":"Component-specific mapping for low-power operation in the presence of variation and aging. In Low-Power Variation-Tolerant Design in Nanometer Silicon. Springer","volume":"12","author":"Gojman Benjamin","year":"2011","unstructured":"Benjamin Gojman , Nikil Mehta , Raphael Rubin , and Andr\u00e9 DeHon . 2011 . Component-specific mapping for low-power operation in the presence of variation and aging. In Low-Power Variation-Tolerant Design in Nanometer Silicon. Springer , Chapter 12 , 381 -- 432 . Benjamin Gojman, Nikil Mehta, Raphael Rubin, and Andr\u00e9 DeHon. 2011. Component-specific mapping for low-power operation in the presence of variation and aging. In Low-Power Variation-Tolerant Design in Nanometer Silicon. Springer, Chapter 12, 381--432.","journal-title":"Chapter"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2435264.2435281"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.5555\/1167704.1167714"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508135"},{"key":"e_1_2_1_13_1","first-page":"1","article-title":"Temperature-dependent device behavior in advanced CMOS technologies","volume":"2","author":"Li Xiaochun","year":"2010","unstructured":"Xiaochun Li , Jialing Tong , and Junfa Mao . 2010 . Temperature-dependent device behavior in advanced CMOS technologies . In ISSSE , Vol. 2. 1 -- 4 . DOI: http:\/\/dx.doi.org\/10.1109\/ISSSE.2010.5606938 10.1109\/ISSSE.2010.5606938 Xiaochun Li, Jialing Tong, and Junfa Mao. 2010. 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