{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:17:51Z","timestamp":1750306671233,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":32,"publisher":"ACM","license":[{"start":{"date-parts":[[2014,5,20]],"date-time":"2014-05-20T00:00:00Z","timestamp":1400544000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100003176","name":"Ministerio de Educaci\u00f3n, Cultura y Deporte","doi-asserted-by":"publisher","award":["TIN2010-18368"],"award-info":[{"award-number":["TIN2010-18368"]}],"id":[{"id":"10.13039\/501100003176","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100002809","name":"Generalitat de Catalunya","doi-asserted-by":"publisher","award":["2009SGR1250"],"award-info":[{"award-number":["2009SGR1250"]}],"id":[{"id":"10.13039\/501100002809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100002418","name":"Intel Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100002418","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2014,5,20]]},"DOI":"10.1145\/2597917.2597937","type":"proceedings-article","created":{"date-parts":[[2014,6,20]],"date-time":"2014-06-20T13:06:05Z","timestamp":1403269565000},"page":"1-10","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Accurate off-line phase classification for HW\/SW co-designed processors"],"prefix":"10.1145","author":[{"given":"Aleksandar","family":"Brankovi\u0107","sequence":"first","affiliation":[{"name":"Universitat Polit\u00e8cnica de Catalunya, Spain"}]},{"given":"Kyriakos","family":"Stavrou","sequence":"additional","affiliation":[{"name":"Intel Barcelona Research Center, Intel Labs Barcelona, Spain"}]},{"given":"Enric","family":"Gibert","sequence":"additional","affiliation":[{"name":"Intel Barcelona Research Center, Intel Labs Barcelona, Spain"}]},{"given":"Antonio","family":"Gonz\u00e1lez","sequence":"additional","affiliation":[{"name":"Universitat Polit\u00e8cnica de Catalunya, Spain and Intel Barcelona Research Center, Intel Labs Barcelona, Spain"}]}],"member":"320","published-online":{"date-parts":[[2014,5,20]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Quick EMUlation tool (http:\/\/http:\/\/www.qemu.org\/).  Quick EMUlation tool (http:\/\/http:\/\/www.qemu.org\/)."},{"volume-title":"Performance Evaluation Corporation. SPEC CPU2006 Benchmarks. (http:\/\/www.spec.org\/cpu2006\/).","key":"e_1_3_2_1_2_1","unstructured":"Standard Performance Evaluation Corporation. SPEC CPU2006 Benchmarks. (http:\/\/www.spec.org\/cpu2006\/). Standard Performance Evaluation Corporation. SPEC CPU2006 Benchmarks. (http:\/\/www.spec.org\/cpu2006\/)."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.34"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1496909.1496921"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/349299.349303"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2482767.2482786"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557141"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/776261.776263"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.931892"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/264107.264126"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1028976.1028999"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1054907.1054914"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1970386.1970390"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.33"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1152154.1152172"},{"key":"e_1_3_2_1_17_1","volume-title":"IBM Microelectronics Division Research Triangle Park NC","author":"The BM.","year":"1999","unstructured":"I BM. The Power PC 440 Core . White-Paper , IBM Microelectronics Division Research Triangle Park NC , 1999 . IBM. The PowerPC 440 Core. White-Paper, IBM Microelectronics Division Research Triangle Park NC, 1999."},{"key":"e_1_3_2_1_18_1","first-page":"253","volume-title":"Proceedings of the 36th annual IEEE\/ACM International Symposium on Microarchitecture, MICRO 36","author":"Kim H.","unstructured":"H. Kim and J. E. Smith . Hardware Support for Control Transfers in Code Caches . In Proceedings of the 36th annual IEEE\/ACM International Symposium on Microarchitecture, MICRO 36 , pages 253 --, 2003. H. Kim and J. E. Smith. Hardware Support for Control Transfers in Code Caches. In Proceedings of the 36th annual IEEE\/ACM International Symposium on Microarchitecture, MICRO 36, pages 253--, 2003."},{"key":"e_1_3_2_1_19_1","volume-title":"January","author":"Klaiber A.","year":"2000","unstructured":"A. Klaiber . The Technology Behind the Crusoe Processors. White paper , January 2000 . A. Klaiber. The Technology Behind the Crusoe Processors. White paper, January 2000."},{"key":"e_1_3_2_1_20_1","volume-title":"Microprocessor Report","author":"Krewell K.","year":"2003","unstructured":"K. Krewell . Transmeta gets more efficeon . Microprocessor Report , 2003 . K. Krewell. Transmeta gets more efficeon. Microprocessor Report, 2003."},{"key":"e_1_3_2_1_21_1","volume-title":"Proceedings of the 2011 Workshop on Infrastructure for Software\/Hardware co-design, WISH '11","author":"Kumar N.","year":"2011","unstructured":"N. Kumar and N. Neelakantam . Indirect Branches in the Transmeta Efficeon Processor . In Proceedings of the 2011 Workshop on Infrastructure for Software\/Hardware co-design, WISH '11 , 2011 . N. Kumar and N. Neelakantam. Indirect Branches in the Transmeta Efficeon Processor. In Proceedings of the 2011 Workshop on Infrastructure for Software\/Hardware co-design, WISH '11, 2011."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.5555\/1153925.1154588"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.scico.2005.07.004"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736026"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/2016604.2016629"},{"key":"e_1_3_2_1_26_1","volume-title":"Proceedings of AMAS workshop, in conjuction with ISCA","author":"Pavlou D.","year":"2011","unstructured":"D. Pavlou , A. Brankovic , R. Kumar , M. Gregori , S. Kyriakos , E. Gibert , and A. Gonzalez . DARCO: Infrastructure for Research on HW\/SW co-designed Virtual Machines . In Proceedings of AMAS workshop, in conjuction with ISCA , 2011 . D. Pavlou, A. Brankovic, R. Kumar, M. Gregori, S. Kyriakos, E. Gibert, and A. Gonzalez. DARCO: Infrastructure for Research on HW\/SW co-designed Virtual Machines. In Proceedings of AMAS workshop, in conjuction with ISCA, 2011."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/2151024.2151046"},{"key":"e_1_3_2_1_28_1","first-page":"2","volume-title":"Proceedings of the 1999 Workshop on Binary Translation, IEEE Computer Society Technical Committee on Computer Architecture Newsletter","author":"Sathaye S.","year":"1999","unstructured":"S. Sathaye : Targeting multi-gigahertz with Binary Translation . In Proceedings of the 1999 Workshop on Binary Translation, IEEE Computer Society Technical Committee on Computer Architecture Newsletter , pages 2 -- 11 , 1999 . S. Sathaye et al. BOA: Targeting multi-gigahertz with Binary Translation. In Proceedings of the 1999 Workshop on Binary Translation, IEEE Computer Society Technical Committee on Computer Architecture Newsletter, pages 2--11, 1999."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605403"},{"key":"e_1_3_2_1_30_1","volume-title":"Virtual Machines: Versatile Platforms for Systems and Processes. The Morgan Kaufmann Series in Computer Architecture and Design","author":"Smith J.","year":"2005","unstructured":"J. Smith and R. Nair . Virtual Machines: Versatile Platforms for Systems and Processes. The Morgan Kaufmann Series in Computer Architecture and Design . 2005 . J. Smith and R. Nair. Virtual Machines: Versatile Platforms for Systems and Processes. The Morgan Kaufmann Series in Computer Architecture and Design. 2005."},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.5555\/2190025.2190070"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859629"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2013.6494980"}],"event":{"name":"CF'14: Computing Frontiers Conference","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"],"location":"Cagliari Italy","acronym":"CF'14"},"container-title":["Proceedings of the 11th ACM Conference on Computing Frontiers"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2597917.2597937","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2597917.2597937","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T07:00:50Z","timestamp":1750230050000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2597917.2597937"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,5,20]]},"references-count":32,"alternative-id":["10.1145\/2597917.2597937","10.1145\/2597917"],"URL":"https:\/\/doi.org\/10.1145\/2597917.2597937","relation":{},"subject":[],"published":{"date-parts":[[2014,5,20]]},"assertion":[{"value":"2014-05-20","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}