{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:17:50Z","timestamp":1750306670231,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":25,"publisher":"ACM","license":[{"start":{"date-parts":[[2014,5,20]],"date-time":"2014-05-20T00:00:00Z","timestamp":1400544000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2014,5,20]]},"DOI":"10.1145\/2597917.2597940","type":"proceedings-article","created":{"date-parts":[[2014,6,20]],"date-time":"2014-06-20T13:06:05Z","timestamp":1403269565000},"page":"1-10","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["SAMO"],"prefix":"10.1145","author":[{"given":"K.","family":"Raghavendra","sequence":"first","affiliation":[{"name":"Indian Institute of Technology Madras, Chennai, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tripti","family":"Warrier","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Madras, Chennai, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Madhu","family":"Mutyam","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Madras, Chennai, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2014,5,20]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.5555\/2337159.2337207"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2005.31"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155663"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485930"},{"key":"e_1_3_2_1_6_1","volume-title":"Computer architecture: A quantitative approach","author":"Hennessy J. L.","year":"2012","unstructured":"J. L. Hennessy and D. A. Patterson . Computer architecture: A quantitative approach . 2012 . J. L. Hennessy and D. A. Patterson. Computer architecture: A quantitative approach. 2012."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/1116644.1116666"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.42"},{"key":"e_1_3_2_1_10_1","first-page":"1","volume-title":"High Performance Computer Architecture (HPCA), 2010 IEEE 16th International Symposium","author":"Kim Y.","year":"2010","unstructured":"Y. Kim , D. Han , O. Mutlu , and M. Harchol-Balter . Atlas: A scalable and high-performance scheduling algorithm for multiple memory controllers . In High Performance Computer Architecture (HPCA), 2010 IEEE 16th International Symposium , pages 1 -- 12 , 2010 . Y. Kim, D. Han, O. Mutlu, and M. Harchol-Balter. Atlas: A scalable and high-performance scheduling algorithm for multiple memory controllers. In High Performance Computer Architecture (HPCA), 2010 IEEE 16th International Symposium, pages 1--12, 2010."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6168945"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155664"},{"key":"e_1_3_2_1_13_1","unstructured":"N. Muralimanohar R. Balasubramonian and N. P. Jouppi. Cacti 5.3 (rev 174) http:\/\/quid.hpl.hp.com:9081\/cacti\/.  N. Muralimanohar R. Balasubramonian and N. P. Jouppi. Cacti 5.3 (rev 174) http:\/\/quid.hpl.hp.com:9081\/cacti\/."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.7"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/342001.339668"},{"key":"e_1_3_2_1_16_1","first-page":"399","volume-title":"Proceedings of the 36th Annual IEEE\/ACM International Symposium on Microarchitecture, MICRO 36","author":"Sethumadhavan S.","unstructured":"S. Sethumadhavan , R. Desikan , D. Burger , C. R. Moore , and S. W. Keckler . Scalable hardware memory disambiguation for high ilp processors . In Proceedings of the 36th Annual IEEE\/ACM International Symposium on Microarchitecture, MICRO 36 , pages 399 --, Washington, DC, USA, 2003. IEEE Computer Society. S. Sethumadhavan, R. Desikan, D. Burger, C. R. Moore, and S. W. Keckler. Scalable hardware memory disambiguation for high ilp processors. In Proceedings of the 36th Annual IEEE\/ACM International Symposium on Microarchitecture, MICRO 36, pages 399--, Washington, DC, USA, 2003. IEEE Computer Society."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2005.29"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.39"},{"key":"e_1_3_2_1_19_1","volume-title":"Modern processor design: Fundamentals of superscalar processors","author":"Shen J. P.","year":"2005","unstructured":"J. P. Shen and M. H. Lipasti . Modern processor design: Fundamentals of superscalar processors . 2005 . J. P. Shen and M. H. Lipasti. Modern processor design: Fundamentals of superscalar processors. 2005."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/384264.379244"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798280"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.26"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.47"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.44"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250696"}],"event":{"name":"CF'14: Computing Frontiers Conference","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"],"location":"Cagliari Italy","acronym":"CF'14"},"container-title":["Proceedings of the 11th ACM Conference on Computing Frontiers"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2597917.2597940","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2597917.2597940","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T07:00:50Z","timestamp":1750230050000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2597917.2597940"}},"subtitle":["store aware memory optimizations"],"short-title":[],"issued":{"date-parts":[[2014,5,20]]},"references-count":25,"alternative-id":["10.1145\/2597917.2597940","10.1145\/2597917"],"URL":"https:\/\/doi.org\/10.1145\/2597917.2597940","relation":{},"subject":[],"published":{"date-parts":[[2014,5,20]]},"assertion":[{"value":"2014-05-20","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}