{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:18:05Z","timestamp":1750306685525,"version":"3.41.0"},"reference-count":31,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2014,5,1]],"date-time":"2014-05-01T00:00:00Z","timestamp":1398902400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2014,5]]},"abstract":"<jats:p>\n            The quest for technologies with superior device characteristics has showcased\n            <jats:italic>Carbon-Nanotube Field-Effect Transistors<\/jats:italic>\n            (CNFET) into limelight. In this work we present physical design techniques to improve the yield of CNFET circuits in the presence of\n            <jats:italic>Carbon Nanotube<\/jats:italic>\n            (CNT) imperfections. Various layout schemes are studied for enhancing the yield of CNFET standard cell library. With the help of existing ASIC design flow, we perform system-level benchmarking of CNFET circuits and compare them to CMOS circuits at various technology nodes. With CNFET technology, we observe maximum performance gains for circuits with gate-dominated delays. Averaged across various benchmarks at 16 nm, we report 8\u00d7 improvement in\n            <jats:italic>Energy-Delay-Product<\/jats:italic>\n            (EDP) with CNFET circuits when compared to CMOS counterpart. We also study the performance of a complete OpenRISC processor, where we see 1.5\u00d7 improvement in EDP over CMOS at 16 nm technology node. Voltage scaling enabled by CNFETs can be explored in the future for further performance benefits.\n          <\/jats:p>","DOI":"10.1145\/2600073","type":"journal-article","created":{"date-parts":[[2014,5,27]],"date-time":"2014-05-27T12:56:59Z","timestamp":1401195419000},"page":"1-19","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits"],"prefix":"10.1145","volume":"10","author":[{"given":"Shashikanth","family":"Bobba","sequence":"first","affiliation":[{"name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Switzerland"}]},{"given":"Jie","family":"Zhang","sequence":"additional","affiliation":[{"name":"Stanford University, Stanford, CA"}]},{"given":"Pierre-Emmanuel","family":"Gaillardon","sequence":"additional","affiliation":[{"name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Switzerland"}]},{"given":"H.-S. Philip","family":"Wong","sequence":"additional","affiliation":[{"name":"Stanford University, Stanford, CA"}]},{"given":"Subhasish","family":"Mitra","sequence":"additional","affiliation":[{"name":"Stanford University, Stanford, CA"}]},{"given":"Giovanni de","family":"Micheli","sequence":"additional","affiliation":[{"name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Switzerland"}]}],"member":"320","published-online":{"date-parts":[[2014,6,2]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"crossref","unstructured":"P. Avouris Z. Chen and V. Perebeinos. 2007. Carbon-based electronics. Nature Nanotech. 605--615.  P. Avouris Z. Chen and V. Perebeinos. 2007. Carbon-based electronics. Nature Nanotech. 605--615.","DOI":"10.1038\/nnano.2007.300"},{"volume-title":"Proceedings of the Conference on Design, Automation and Test in Europe. European Design and Automation Association, 616--621","author":"Bobba S.","key":"e_1_2_1_2_1","unstructured":"S. Bobba , J. Zhang , A. Pullini , D. Atienza , and G. De Micheli . 2009. Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis . In Proceedings of the Conference on Design, Automation and Test in Europe. European Design and Automation Association, 616--621 . S. Bobba, J. Zhang, A. Pullini, D. Atienza, and G. De Micheli. 2009. Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis. In Proceedings of the Conference on Design, Automation and Test in Europe. European Design and Automation Association, 616--621."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382665"},{"key":"e_1_2_1_4_1","unstructured":"Synopsys Design Compiler 2012. http:\/\/www.synopsys.com.  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VMR: VLSI-compatible metallic carbon nanotube removal for imperfection-immune cascaded multi-stage digital logic circuits using carbon nanotube FETs . In Proceedings of the IEEE International Electron Devices Meeting. 1--4. N. Patil, A. Lin, J. Zhang, H. Wei, K. Anderson, H. S. Wong, and S. Mitra. 2009c. VMR: VLSI-compatible metallic carbon nanotube removal for imperfection-immune cascaded multi-stage digital logic circuits using carbon nanotube FETs. In Proceedings of the IEEE International Electron Devices Meeting. 1--4."},{"key":"e_1_2_1_20_1","volume-title":"Digital Integrated Circuits","volume":"2","author":"Rabaey J. M.","unstructured":"J. M. Rabaey , A. P. Chandrakasan , and B. Nikolic . 2002 . Digital Integrated Circuits , Vol. 2 , Prentice Hall, Englewood Cliffs, NJ. J. M. Rabaey, A. P. Chandrakasan, and B. Nikolic. 2002. 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Akinwande , C. Beasley , Y. Chai , H. Y. Chen , and J. Zhang . 2011. Carbon nanotube electronics: -Materials, devices, circuits, design, modeling, and performance projection . In Proceedings of the IEEE International Electron Devices Meeting. H. S. Wong, S. Mitra, D. Akinwande, C. Beasley, Y. Chai, H. Y. Chen, and J. Zhang. 2011. Carbon nanotube electronics: -Materials, devices, circuits, design, modeling, and performance projection. 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