{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:16:25Z","timestamp":1763468185637,"version":"3.41.0"},"reference-count":42,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2014,5,1]],"date-time":"2014-05-01T00:00:00Z","timestamp":1398902400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100003407","name":"Ministero dell'Istruzione, dell'Universit\u00e0 e della Ricerca","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003407","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2014,5]]},"abstract":"<jats:p>\n            Nanophotonic is a promising solution for on-chip interconnection due to its intrinsic low-latency and low-power features. Future tiled chip multiprocessors (CMPs) for rich\n            <jats:italic>client<\/jats:italic>\n            devices can receive energy benefits from this technology but we show that great care has to be put in the integration of the various involved facets to avoid queuing and serialization issues and obtain the rated potential advantages.\n          <\/jats:p>\n          <jats:p>We evaluate different management strategies for accessing a simple, shared photonic path (ring), working in conjunctions with a standard electronic mesh or alone, in a tiled CMP. Our results highlight that a careful selection of the most latency-critical messages to be routed in photonics and the use of a conflict-free access scheme is crucial for obtaining performance\/power advantages when the available bandwidth is limited.<\/jats:p>\n          <jats:p>We identify the design point where all the traffic can be routed on the photonic path and thus the electronic network can be suppressed. At this point, the ring achieves 20--25% speedup and 84% energy consumption improvement over the electronic baseline.<\/jats:p>\n          <jats:p>Then we investigate the same trade-offs when the number of rings is increased up to eight, allowing to raise performance benefits up to 40% or reaching up to 80% energy reduction. We finally explore the effects of deploying a given optical parallelism split between a higher number of waveguides for further improving energy savings.<\/jats:p>","DOI":"10.1145\/2602155","type":"journal-article","created":{"date-parts":[[2014,5,27]],"date-time":"2014-05-27T12:56:59Z","timestamp":1401195419000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":37,"title":["Design Options for Optical Ring Interconnect in Future Client Devices"],"prefix":"10.1145","volume":"10","author":[{"given":"Paolo","family":"Grani","sequence":"first","affiliation":[{"name":"University of Siena, Siena, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sandro","family":"Bartolini","sequence":"additional","affiliation":[{"name":"University of Siena, Siena, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2014,6,2]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"AMD. 2013. AMD Opteron 6000 Series Platform. http:\/\/www.amd.com\/US\/PRODUCTS\/SERVER\/PROCESSORS\/6000-SERIES-PLATFORM\/Pages\/6000-series-platform.aspx.  AMD. 2013. AMD Opteron 6000 Series Platform. http:\/\/www.amd.com\/US\/PRODUCTS\/SERVER\/PROCESSORS\/6000-SERIES-PLATFORM\/Pages\/6000-series-platform.aspx."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629435.1629453"},{"volume-title":"Proceedings of the 13th International Symposium on Quality Electronic Design. 78--83","author":"Bahirat S.","key":"e_1_2_1_3_1"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/309847.310093"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306792"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2012.13"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2489068.2489070"},{"key":"e_1_2_1_8_1","first-page":"2","article-title":"Designing chip-level nanophotonic interconnection networks","volume":"2","author":"Batten C.","year":"2012","journal-title":"IEEE J. Emerging Sel. Top. Circuits Syst."},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1088\/0034-4885\/75\/4\/046402"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.82"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.5555\/1266366.1266600"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1364\/JOCN.4.000189"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1814433.1814453"},{"volume-title":"Proceedings of the Ottawa Linux Summit.","year":"2002","author":"Franke Hubertus","key":"e_1_2_1_15_1"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1984.12943"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2009.5071458"},{"key":"e_1_2_1_18_1","unstructured":"ITRS. 2011. International Technology Roadmap for Semiconductors - Interconnection.  ITRS. 2011. International Technology Roadmap for Semiconductors - Interconnection."},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2091686"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/605432.605420"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/WAINA.2011.23"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854332"},{"volume-title":"Proceedings of the Design, Automation Test in Europe Conference and Exhibition. 1--6.","author":"Beux S. Le","key":"e_1_2_1_23_1"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/1594233.1594305"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.15"},{"key":"e_1_2_1_26_1","unstructured":"Ian O'Connor and Frederic Gaffiot. 2004. On-chip optical interconnect for low-power. In Ultra-Low Power Electronics and Design E. Macii (Ed.) Kluwer Dordrecht.  Ian O'Connor and Frederic Gaffiot. 2004. On-chip optical interconnect for low-power. In Ultra-Low Power Electronics and Design E. Macii (Ed.) Kluwer Dordrecht."},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/2107763.2107772"},{"volume-title":"Proceedings of the IEEE 16th International Symposium onHigh Performance Computer Architecture (HPCA). 1--12","author":"Pan Yan","key":"e_1_2_1_28_1"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555808"},{"volume-title":"Proceedings of the 16th Asia and South Pacific Design Automation Conference (ASP-DAC). 345--350","author":"Pasricha S.","key":"e_1_2_1_30_1"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/HOTI.2008.20"},{"volume-title":"Proceedings of the International Conference on Computer Design (CDES'08)","author":"Ros Alberto","key":"e_1_2_1_32_1"},{"key":"e_1_2_1_33_1","unstructured":"Samsung. 2013. Samsung Exynos 5 Octa. http:\/\/www.samsung.com.  Samsung. 2013. Samsung Exynos 5 Octa. http:\/\/www.samsung.com."},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.78"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1049\/ecej:19990406"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.31"},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.910957"},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669152"},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/1394608.1382135"},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/225830.223990"},{"key":"e_1_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/1995896.1995941"},{"key":"e_1_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1364\/OE.19.005172"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2602155","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2602155","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T07:00:47Z","timestamp":1750230047000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2602155"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,5]]},"references-count":42,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2014,5]]}},"alternative-id":["10.1145\/2602155"],"URL":"https:\/\/doi.org\/10.1145\/2602155","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"type":"print","value":"1550-4832"},{"type":"electronic","value":"1550-4840"}],"subject":[],"published":{"date-parts":[[2014,5]]},"assertion":[{"value":"2013-09-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2014-02-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2014-06-02","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}