{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:18:11Z","timestamp":1750306691546,"version":"3.41.0"},"reference-count":30,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2014,6,1]],"date-time":"2014-06-01T00:00:00Z","timestamp":1401580800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100001659","name":"Deutsche Forschungsgemeinschaft","doi-asserted-by":"publisher","award":["BE 1176\/14-2 and WU 245\/11-1"],"award-info":[{"award-number":["BE 1176\/14-2 and WU 245\/11-1"]}],"id":[{"id":"10.13039\/501100001659","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2014,6]]},"abstract":"<jats:p>Logic and fault simulation are essential techniques in electronic design automation. The accuracy of standard simulation algorithms is compromised by unknown or X-values. This results in a pessimistic overestimation of X-valued signals in the circuit and a pessimistic underestimation of fault coverage.<\/jats:p>\n          <jats:p>This work proposes efficient algorithms for combinational and sequential logic as well as for stuck-at and transition-delay fault simulation that are free of any simulation pessimism in presence of unknowns. The SAT-based algorithms exactly classifiy all signal states. During fault simulation, each fault is accurately classified as either undetected, definitely detected, or possibly detected.<\/jats:p>\n          <jats:p>The pessimism with respect to unknowns present in classic algorithms is thoroughly investigated in the experimental results on benchmark circuits. The applicability of the proposed algorithms is demonstrated on larger industrial circuits. The results show that, by accurate analysis, the number of detected faults can be significantly increased without increasing the test-set size.<\/jats:p>","DOI":"10.1145\/2611760","type":"journal-article","created":{"date-parts":[[2014,6,17]],"date-time":"2014-06-17T12:38:13Z","timestamp":1403008693000},"page":"1-17","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["Exact Logic and Fault Simulation in Presence of Unknowns"],"prefix":"10.1145","volume":"19","author":[{"given":"Dominik","family":"Erb","sequence":"first","affiliation":[{"name":"University of Freiburg, Freiburg, Germany"}]},{"given":"Michael A.","family":"Kochte","sequence":"additional","affiliation":[{"name":"University of Stuttgart, Stuttgart, Germany"}]},{"given":"Matthias","family":"Sauer","sequence":"additional","affiliation":[{"name":"University of Freiburg, Freiburg, Germany"}]},{"given":"Stefan","family":"Hillebrecht","sequence":"additional","affiliation":[{"name":"University of Freiburg, Freiburg, Germany"}]},{"given":"Tobias","family":"Schubert","sequence":"additional","affiliation":[{"name":"University of Freiburg, Freiburg, Germany"}]},{"given":"Hans-Joachim","family":"Wunderlich","sequence":"additional","affiliation":[{"name":"University of Stuttgart, Stuttgart, Germany"}]},{"given":"Bernd","family":"Becker","sequence":"additional","affiliation":[{"name":"University of Freiburg, Freiburg, Germany"}]}],"member":"320","published-online":{"date-parts":[[2014,6,23]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1987.1270316"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008376522451"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1986.1676819"},{"volume-title":"Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD'89)","author":"Carter J. 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In Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD'87). 404--407."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2042905"},{"volume-title":"Proceedings of the 17th IEEE European Test Symposium (ETS'12)","author":"Hillebrecht S.","key":"e_1_2_1_7_1","unstructured":"S. Hillebrecht , M. A. Kochte , H.-J. Wunderlich , and B. Becker . 2012. Exact stuck-at fault classification in presence of unknowns . In Proceedings of the 17th IEEE European Test Symposium (ETS'12) . 98--103. S. Hillebrecht, M. A. Kochte, H.-J. Wunderlich, and B. Becker. 2012. Exact stuck-at fault classification in presence of unknowns. In Proceedings of the 17th IEEE European Test Symposium (ETS'12). 98--103."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/832300.836597"},{"volume-title":"Proceeding of the IEEE European Test Symposium (ETS'04)","author":"Kajihara S.","key":"e_1_2_1_9_1","unstructured":"S. Kajihara , K. Saluja , and S. M. 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An efficient, forward fault simulation algorithm based on the parallel pattern single fault propagation . In Proceedings of the International Test Conference (ITC'91) . IEEE Computer Society, 946--955. H. K. Lee and D. S. Ha. 1991. An efficient, forward fault simulation algorithm based on the parallel pattern single fault propagation. In Proceedings of the International Test Conference (ITC'91). IEEE Computer Society, 946--955."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.823341"},{"volume-title":"Proceedings of the IEEE International Test Conference (ITC'03)","author":"Naruse M.","key":"e_1_2_1_17_1","unstructured":"M. Naruse , I. Pomeranz , S. M. Reddy , and S. Kundu . 2003. On-chip compression of output responses with unknown values using lfsr reseeding . In Proceedings of the IEEE International Test Conference (ITC'03) . IEEE Computer Society, 1060--1068. M. Naruse, I. Pomeranz, S. M. Reddy, and S. Kundu. 2003. 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