{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:18:11Z","timestamp":1750306691610,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":30,"publisher":"ACM","license":[{"start":{"date-parts":[[2014,6,15]],"date-time":"2014-06-15T00:00:00Z","timestamp":1402790400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2014,6,15]]},"DOI":"10.1145\/2611765.2611776","type":"proceedings-article","created":{"date-parts":[[2014,5,30]],"date-time":"2014-05-30T18:18:31Z","timestamp":1401473911000},"page":"1-5","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["Memory bandwidth reservation in the cloud to avoid information leakage in the memory controller"],"prefix":"10.1145","author":[{"given":"Akhila","family":"Gundu","sequence":"first","affiliation":[{"name":"University of Utah"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gita","family":"Sreekumar","sequence":"additional","affiliation":[{"name":"University of Utah"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ali","family":"Shafiee","sequence":"additional","affiliation":[{"name":"University of Utah"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Seth","family":"Pugsley","sequence":"additional","affiliation":[{"name":"University of Utah"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hardik","family":"Jain","sequence":"additional","affiliation":[{"name":"University of Texas, Austin"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rajeev","family":"Balasubramonian","sequence":"additional","affiliation":[{"name":"University of Utah"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mohit","family":"Tiwari","sequence":"additional","affiliation":[{"name":"University of Texas, Austin"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2014,6,15]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Wind River Simics Full System Simulator. http:\/\/www.windriver.com\/products\/simics\/.  Wind River Simics Full System Simulator. http:\/\/www.windriver.com\/products\/simics\/."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1314466.1314469"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1007\/11967668_15"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1229285.1266999"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNET.2008.2008646"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTCSA.2008.21"},{"key":"e_1_3_2_1_7_1","volume-title":"Cache-timing Attacks on AES","author":"Bernstein D. J.","year":"2005","unstructured":"D. J. Bernstein . Cache-timing Attacks on AES , 2005 . D. J. Bernstein. Cache-timing Attacks on AES, 2005."},{"key":"e_1_3_2_1_8_1","volume-title":"USIMM: the Utah SImulated Memory Module. Technical report","author":"Chatterjee N.","year":"2012","unstructured":"N. Chatterjee , R. Balasubramonian , M. Shevgoor , S. Pugsley , A. Udipi , A. Shafiee , K. Sudan , M. Awasthi , and Z. Chishti . USIMM: the Utah SImulated Memory Module. Technical report , University of Utah , 2012 . UUCS-12-002. N. Chatterjee, R. Balasubramonian, M. Shevgoor, S. Pugsley, A. Udipi, A. Shafiee, K. Sudan, M. Awasthi, and Z. Chishti. USIMM: the Utah SImulated Memory Module. Technical report, University of Utah, 2012. UUCS-12-002."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6168943"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1254882.1254886"},{"key":"e_1_3_2_1_11_1","volume-title":"JESD79-4: JEDEC Standard DDR4 SDRAM","author":"JEDEC.","year":"2012","unstructured":"JEDEC. JESD79-4: JEDEC Standard DDR4 SDRAM , 2012 . JEDEC. JESD79-4: JEDEC Standard DDR4 SDRAM, 2012."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798277"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/2337159.2337173"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155664"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.24"},{"key":"e_1_3_2_1_16_1","first-page":"280","volume":"2005","author":"Page D.","year":"2005","unstructured":"D. Page . Partitioned Cache Architecture as a Side-Channel Defence Mechanism. IACR Cryptology e Print Archive , 2005 : 280 , 2005 . D. Page. Partitioned Cache Architecture as a Side-Channel Defence Mechanism. IACR Cryptology ePrint Archive, 2005:280, 2005.","journal-title":"Print Archive"},{"key":"e_1_3_2_1_17_1","volume-title":"Cache Missing for Fun and Profit","author":"Percival C.","year":"2005","unstructured":"C. Percival . Cache Missing for Fun and Profit , 2005 . C. Percival. Cache Missing for Fun and Profit, 2005."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.5555\/1299042.1299052"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/2039370.2039388"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1653662.1653687"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339668"},{"key":"e_1_3_2_1_22_1","volume-title":"Proceedings of EuroSec","author":"Saltaformaggio B.","year":"2013","unstructured":"B. Saltaformaggio , D. Xu , and X. Zhang . BusMonitor: A Hypervisor-Based Solution for Memory Bus Covert Channels . In Proceedings of EuroSec , 2013 . B. Saltaformaggio, D. Xu, and X. Zhang. BusMonitor: A Hypervisor-Based Solution for Memory Bus Covert Channels. In Proceedings of EuroSec, 2013."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370834"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.24"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACSAC.2006.20"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250723"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771781"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485972"},{"key":"e_1_3_2_1_29_1","volume-title":"Whispers in the Hyper-space: High-speed Covert Channel Attacks in the Cloud. In the 21st USENIX Security Symposium (Security '12)","author":"Wu Z.","year":"2012","unstructured":"Z. Wu , Z. Xu , and H. Wang . Whispers in the Hyper-space: High-speed Covert Channel Attacks in the Cloud. In the 21st USENIX Security Symposium (Security '12) , 2012 . Z. Wu, Z. Xu, and H. Wang. Whispers in the Hyper-space: High-speed Covert Channel Attacks in the Cloud. In the 21st USENIX Security Symposium (Security '12), 2012."},{"key":"e_1_3_2_1_30_1","volume-title":"Proceedings of HPCA","author":"Yao Wang A. F.","year":"2014","unstructured":"A. F. Yao Wang and G. E. Suh . Timing Channel Protection for a Shared Memory Controller . In Proceedings of HPCA , 2014 . A. F. Yao Wang and G. E. Suh. Timing Channel Protection for a Shared Memory Controller. In Proceedings of HPCA, 2014."}],"event":{"name":"HASP '14: The Third Workshop on Hardware and Architectural Support for Security and Privacy","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture"],"location":"Minneapolis Minnesota USA","acronym":"HASP '14"},"container-title":["Proceedings of the Third Workshop on Hardware and Architectural Support for Security and Privacy"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2611765.2611776","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2611765.2611776","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T07:01:34Z","timestamp":1750230094000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2611765.2611776"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,6,15]]},"references-count":30,"alternative-id":["10.1145\/2611765.2611776","10.1145\/2611765"],"URL":"https:\/\/doi.org\/10.1145\/2611765.2611776","relation":{},"subject":[],"published":{"date-parts":[[2014,6,15]]},"assertion":[{"value":"2014-06-15","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}