{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:18:11Z","timestamp":1750306691665,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":17,"publisher":"ACM","license":[{"start":{"date-parts":[[2014,6,10]],"date-time":"2014-06-10T00:00:00Z","timestamp":1402358400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2014,6,10]]},"DOI":"10.1145\/2612262.2612267","type":"proceedings-article","created":{"date-parts":[[2014,6,10]],"date-time":"2014-06-10T12:50:25Z","timestamp":1402404625000},"page":"1-8","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Hybrid MPI"],"prefix":"10.1145","author":[{"given":"U. S.","family":"Wickramasinghe","sequence":"first","affiliation":[{"name":"Indiana University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Greg","family":"Bronevetsky","sequence":"additional","affiliation":[{"name":"Lawrence Livermore National Laboratory"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andrew","family":"Lumsdaine","sequence":"additional","affiliation":[{"name":"Indiana University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andrew","family":"Friedley","sequence":"additional","affiliation":[{"name":"Intel Corporation"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2014,6,10]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"crossref","unstructured":"The OpenCL specification version 1.0 2009. The OpenCL specification version 1.0 2009.","DOI":"10.1109\/HOTCHIPS.2009.7478338"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2503210.2503294"},{"key":"e_1_3_2_1_3_1","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"132","DOI":"10.1007\/978-3-642-15646-5_14","volume-title":"Recent Advances in the Message Passing Interface","author":"Hoefler T.","year":"2010","unstructured":"T. Hoefler and S. Gottlieb . Parallel zero-copy algorithms for fast fourier transform and conjugate gradient using mpi datatypes . In R. Keller, E. Gabriel, M. Resch, and J. Dongarra, editors, Recent Advances in the Message Passing Interface , volume 6305 of Lecture Notes in Computer Science , pages 132 -- 141 . Springer Berlin Heidelberg , 2010 . T. Hoefler and S. Gottlieb. Parallel zero-copy algorithms for fast fourier transform and conjugate gradient using mpi datatypes. In R. Keller, E. Gabriel, M. Resch, and J. Dongarra, editors, Recent Advances in the Message Passing Interface, volume 6305 of Lecture Notes in Computer Science, pages 132--141. Springer Berlin Heidelberg, 2010."},{"key":"e_1_3_2_1_4_1","unstructured":"Intel Corporation. Intel manycore platform software stack (mpss). http:\/\/software.intel.com\/en-us\/articles\/intel-manycore-platform-software-stack-mpss. Intel Corporation. Intel manycore platform software stack (mpss). http:\/\/software.intel.com\/en-us\/articles\/intel-manycore-platform-software-stack-mpss."},{"key":"e_1_3_2_1_5_1","unstructured":"Intel Corporation. Intel mpi library - documentation. http:\/\/software.intel.com\/en-us\/articles\/intel-mpi-library-documentation. Intel Corporation. Intel mpi library - documentation. http:\/\/software.intel.com\/en-us\/articles\/intel-mpi-library-documentation."},{"key":"e_1_3_2_1_6_1","unstructured":"Intel Corporation. Intel xeon phi coprocessor system software developers guide. http:\/\/www.intel.com\/content\/dam\/www\/public\/us\/en\/documents\/product-briefs\/xeon-phi-coprocessor-system-software-developers-guide.pdf. Intel Corporation. Intel xeon phi coprocessor system software developers guide. http:\/\/www.intel.com\/content\/dam\/www\/public\/us\/en\/documents\/product-briefs\/xeon-phi-coprocessor-system-software-developers-guide.pdf."},{"key":"e_1_3_2_1_7_1","unstructured":"LLNL. The presta stress benchmark v1.2. http:\/\/asc.llnl.gov\/computing\\_resources\/purple\/archive\/benchmarks\/presta\/. LLNL. The presta stress benchmark v1.2. http:\/\/asc.llnl.gov\/computing\\_resources\/purple\/archive\/benchmarks\/presta\/."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/103727.103729"},{"key":"e_1_3_2_1_9_1","volume-title":"September 4","author":"Forum MPI","year":"2009","unstructured":"MPI Forum . MPI: A message-passing interface standard. version 2.2 , September 4 2009 . MPI Forum. MPI: A message-passing interface standard. version 2.2, September 4 2009."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1365490.1365500"},{"key":"e_1_3_2_1_11_1","unstructured":"NUDT. Tianhe-2 supercomputer. http:\/\/www.top500.org\/. NUDT. Tianhe-2 supercomputer. http:\/\/www.top500.org\/."},{"key":"e_1_3_2_1_12_1","volume-title":"May","author":"Architecture Review Board MP","year":"2008","unstructured":"Open MP Architecture Review Board . OpenMP application program interface version 3.0 , May 2008 . OpenMP Architecture Review Board. OpenMP application program interface version 3.0, May 2008."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/2503210.2503288"},{"key":"e_1_3_2_1_14_1","unstructured":"R. Rahman. Intel xeon phi coprocessor architecture for software developers. http:\/\/software.intel.com\/en-us\/articles\/intel-xeon-phi-coprocessor-architecture-for-software-developers. R. Rahman. Intel xeon phi coprocessor architecture for software developers. http:\/\/software.intel.com\/en-us\/articles\/intel-xeon-phi-coprocessor-architecture-for-software-developers."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/2493123.2462916"},{"key":"e_1_3_2_1_16_1","unstructured":"F. Roth. Avoiding potential problems - memory limits on the intel xeon phi coprocessor. http:\/\/software.intel.com\/en-us\/blogs\/2013\/07\/11\/avoiding-potential-problems-memory-limits-on-the-intelr-xeon-phitm-coprocessor. F. Roth. Avoiding potential problems - memory limits on the intel xeon phi coprocessor. http:\/\/software.intel.com\/en-us\/blogs\/2013\/07\/11\/avoiding-potential-problems-memory-limits-on-the-intelr-xeon-phitm-coprocessor."},{"key":"e_1_3_2_1_17_1","unstructured":"TACC. Stampede supercomputer. http:\/\/www.top500.org\/system\/177931. TACC. Stampede supercomputer. http:\/\/www.top500.org\/system\/177931."}],"event":{"name":"ROSS '14: Runtime and Operating Systems for Supercomputers","sponsor":["SPCL Scalable Parallel Computing Laboratory","SIGHPC ACM Special Interest Group on High Performance Computing, Special Interest Group on High Performance Computing"],"location":"Munich Germany","acronym":"ROSS '14"},"container-title":["Proceedings of the 4th International Workshop on Runtime and Operating Systems for Supercomputers"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2612262.2612267","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2612262.2612267","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T07:01:34Z","timestamp":1750230094000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2612262.2612267"}},"subtitle":["a case study on the Xeon Phi platform"],"short-title":[],"issued":{"date-parts":[[2014,6,10]]},"references-count":17,"alternative-id":["10.1145\/2612262.2612267","10.1145\/2612262"],"URL":"https:\/\/doi.org\/10.1145\/2612262.2612267","relation":{},"subject":[],"published":{"date-parts":[[2014,6,10]]},"assertion":[{"value":"2014-06-10","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}