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Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2014,6]]},"abstract":"<jats:p>\n            To fully exploit the capabilities of runtime reconfigurable FPGAs in self-aware systems, design tools are required that exceed the capabilities of present vendor design tools. Such tools must allow the implementation of scalable reconfigurable systems with various different partial modules that might be loaded to different positions of the device at runtime. This comprises several complex tasks, including floorplanning, communication architecture synthesis, physical constraints generation, physical implementation, and timing verification all the way down to the final bitstream generation. In this article, we present how our\n            <jats:sc>GoAhead<\/jats:sc>\n            framework helps in implementing self-aware systems on FPGAs with a minimum of user interaction.\n          <\/jats:p>","DOI":"10.1145\/2617597","type":"journal-article","created":{"date-parts":[[2014,7,1]],"date-time":"2014-07-01T14:23:02Z","timestamp":1404224582000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["Design Tools for Implementing Self-Aware and Fault-Tolerant Systems on FPGAs"],"prefix":"10.1145","volume":"7","author":[{"given":"Christian","family":"Beckhoff","sequence":"first","affiliation":[{"name":"University of Oslo, Norway"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dirk","family":"Koch","sequence":"additional","affiliation":[{"name":"The University of Manchester, U.K"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jim","family":"Torresen","sequence":"additional","affiliation":[{"name":"University of Oslo, Norway"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2014,7,4]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2007.29"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2010.117"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2011.144"},{"volume-title":"Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip. 1--8.","author":"Beckhoff C.","key":"e_1_2_1_4_1"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2012.17"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-36424-2_26"},{"key":"e_1_2_1_7_1","unstructured":"M. Bourgeault. 2011. Altera's partial reconfiguration flow. www.eecg.utoronto.ca\/&sim;jayar\/FPGAseminar\/FPGA_Bourgeault_June23_2011.pdf.  M. Bourgeault. 2011. Altera's partial reconfiguration flow. www.eecg.utoronto.ca\/&sim;jayar\/FPGAseminar\/FPGA_Bourgeault_June23_2011.pdf."},{"volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications. 1--6.","author":"Campregher N.","key":"e_1_2_1_8_1"},{"volume-title":"Proceedings of the Workshop on Reconfigurable Computing Education at ISVLSI.","author":"Claus C.","key":"e_1_2_1_9_1"},{"key":"e_1_2_1_10_1","unstructured":"CosReCos. 2012. CosReCos ProjectWebsite: www.mn.uio.no\/ifi\/english\/research\/projects\/cosrecos\/.  CosReCos. 2012. CosReCos ProjectWebsite: www.mn.uio.no\/ifi\/english\/research\/projects\/cosrecos\/."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2012.18"},{"volume-title":"Algol 60 Translation: An Algol 60 Translator for the X1. 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