{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T15:48:42Z","timestamp":1780674522432,"version":"3.54.1"},"publisher-location":"New York, NY, USA","reference-count":37,"publisher":"ACM","license":[{"start":{"date-parts":[[2014,8,24]],"date-time":"2014-08-24T00:00:00Z","timestamp":1408838400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["1117025"],"award-info":[{"award-number":["1117025"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2014,8,24]]},"DOI":"10.1145\/2628071.2628104","type":"proceedings-article","created":{"date-parts":[[2014,8,21]],"date-time":"2014-08-21T12:19:23Z","timestamp":1408623563000},"page":"381-392","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":112,"title":["COLORIS"],"prefix":"10.1145","author":[{"given":"Ying","family":"Ye","sequence":"first","affiliation":[{"name":"Boston University, Boston, MA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Richard","family":"West","sequence":"additional","affiliation":[{"name":"Boston University, Boston, MA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zhuoqun","family":"Cheng","sequence":"additional","affiliation":[{"name":"Boston University, Boston, MA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ye","family":"Li","sequence":"additional","affiliation":[{"name":"Boston University, Boston, MA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2014,8,24]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/774789.774805"},{"key":"e_1_3_2_1_2_1","first-page":"213","volume-title":"Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques","author":"Beckmann N.","year":"2013","unstructured":"N. Beckmann and D. Sanchez . Jigsaw: Scalable software-defined caches . In Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques , pages 213 -- 224 , Piscataway, NJ, USA , 2013 . N. Beckmann and D. Sanchez. Jigsaw: Scalable software-defined caches. In Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, pages 213--224, Piscataway, NJ, USA, 2013."},{"key":"e_1_3_2_1_3_1","volume-title":"USA","author":"Bray B. K.","year":"1990","unstructured":"B. K. Bray , W. L. Lunch , and M. J. Flynn . Page allocation to reduce access time of physical caches. Technical report, Stanford, CA , USA , 1990 . B. K. Bray, W. L. Lunch, and M. J. Flynn. Page allocation to reduce access time of physical caches. Technical report, Stanford, CA, USA, 1990."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/237090.237195"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337523"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.31"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1966445.1966468"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346180"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1088149.1088154"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1006209.1006246"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2151003"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/138873.138876"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/1025127.1026001"},{"key":"e_1_3_2_1_14_1","first-page":"367","volume-title":"Proceedings of the 14th International Symposium on High-Performance Computer Architecture","author":"Lin J.","year":"2008","unstructured":"J. Lin , Q. Lu , X. Ding , Z. Zhang , X. Zhang , and P. Sadayappan . Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems . In Proceedings of the 14th International Symposium on High-Performance Computer Architecture , pages 367 -- 378 , 2008 . J. Lin, Q. Lu, X. Ding, Z. Zhang, X. Zhang, and P. Sadayappan. Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems. In Proceedings of the 14th International Symposium on High-Performance Computer Architecture, pages 367--378, 2008."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2004.10017"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2009.35"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2013.6531078"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.5555\/2014698.2014862"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.49"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1152154.1152160"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339685"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000073"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/305138.305189"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771796"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/1654059.1654066"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.5555\/874076.876484"},{"key":"e_1_3_2_1_27_1","first-page":"116","volume-title":"Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems","author":"Suh G. E.","year":"2001","unstructured":"G. E. Suh , L. Rudolph , and S. Devadas . Dynamic cache partitioning for simultaneous multithreading systems . In Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems , pages 116 -- 127 , 2001 . G. E. Suh, L. Rudolph, and S. Devadas. Dynamic cache partitioning for simultaneous multithreading systems. In Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems, pages 116--127, 2001."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1023\/B:SUPE.0000014800.27383.8f"},{"key":"e_1_3_2_1_29_1","volume-title":"Proceedings of the Workshop on the Interaction between Operating Systems and Computer Architecture","author":"Tam D.","year":"2007","unstructured":"D. Tam , R. Azimi , L. Soares , and M. Stumm . Managing shared L2 caches on multicore systems in software . In Proceedings of the Workshop on the Interaction between Operating Systems and Computer Architecture , 2007 . D. Tam, R. Azimi, L. Soares, and M. Stumm. Managing shared L2 caches on multicore systems in software. In Proceedings of the Workshop on the Interaction between Operating Systems and Computer Architecture, 2007."},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508259"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/325164.325161"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/1899928.1899931"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1201\/b15268-12"},{"key":"e_1_3_2_1_34_1","volume-title":"the 2nd Workshop on Chip Multiprocessor Memory Systems and Interconnects","author":"Xie Y.","year":"2008","unstructured":"Y. Xie and G. Loh . Dynamic classification of program memory behaviors in CMPs . In the 2nd Workshop on Chip Multiprocessor Memory Systems and Interconnects , 2008 . Y. Xie and G. Loh. Dynamic classification of program memory behaviors in CMPs. In the 2nd Workshop on Chip Multiprocessor Memory Systems and Interconnects, 2008."},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/1519065.1519076"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/1399972.1399982"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/1024393.1024415"}],"event":{"name":"PACT '14: International Conference on Parallel Architectures and Compilation","location":"Edmonton AB Canada","acronym":"PACT '14","sponsor":["IFIP WG 10.3 IFIP WG 10.3","SIGARCH ACM Special Interest Group on Computer Architecture","IEEE CS TCPP IEEE Computer Society Technical Committee on Parallel Processing","IEEE CS TCAA IEEE CS technical committee on architectural acoustics"]},"container-title":["Proceedings of the 23rd international conference on Parallel architectures and compilation"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2628071.2628104","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2628071.2628104","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T07:19:38Z","timestamp":1750231178000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2628071.2628104"}},"subtitle":["a dynamic cache partitioning system using page coloring"],"short-title":[],"issued":{"date-parts":[[2014,8,24]]},"references-count":37,"alternative-id":["10.1145\/2628071.2628104","10.1145\/2628071"],"URL":"https:\/\/doi.org\/10.1145\/2628071.2628104","relation":{},"subject":[],"published":{"date-parts":[[2014,8,24]]},"assertion":[{"value":"2014-08-24","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}