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Syst."],"published-print":{"date-parts":[[2014,10,6]]},"abstract":"<jats:p>Optimizing energy consumption for electronic systems has been an important design consideration. Multipower domain design is widely used for low-power and high-performance applications. Data transfer between power domains needs a cross-power domain interface (CPDI). The existing level-conversion flip-flop (LCFF) structures all need dual power rails, which lead to large area and performance overhead. In this article, we propose a scanable CPDI circuit, utilizing monolithic 3D technology. This interface functions as a flip-flop and provides reliable data conversion from one power domain to another. It has a built-in scan feature, which makes it a testable design. Our design separates power rails in each tier, substantially reducing physical design complexity and area penalty. The design is implemented in a 20nm, 28nm, and 45nm low-power technology. It shows a 20%--35% smaller insertion delay compared to normal designs. This proposed design also shows scalability and better energy consumption than previous LCFF circuits.<\/jats:p>","DOI":"10.1145\/2629516","type":"journal-article","created":{"date-parts":[[2014,10,7]],"date-time":"2014-10-07T12:57:47Z","timestamp":1412686667000},"page":"1-17","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Testable cross-power domain interface (CPDI) circuit design in monolithic 3D technology"],"prefix":"10.1145","volume":"11","author":[{"given":"Jing","family":"Xie","sequence":"first","affiliation":[{"name":"The Pennsylvania State University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yang","family":"Du","sequence":"additional","affiliation":[{"name":"Qualcomm Corporation Research and Development"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuan","family":"Xie","sequence":"additional","affiliation":[{"name":"The Pennsylvania State University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2014,10,6]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2012.6242496"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131506"},{"volume-title":"Proceedings of the IEEE International 3D Systems Integration Conference. 1--4.","author":"Bobba S.","key":"e_1_2_1_3_1","unstructured":"S. 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System level analysis of fast, per-core DVFS using on-chip switching regulators . In Proceedings of the IEEE 14th International Symposium on High Performance Computer Architecture. 123--134 . Wonyoung Kim, M. S. Gupta, Gu-Yeon Wei, et al. 2008. System level analysis of fast, per-core DVFS using on-chip switching regulators. In Proceedings of the IEEE 14th International Symposium on High Performance Computer Architecture. 123--134."},{"volume-title":"Proceedings of the IEEE International Solid-State Circuits Conference. 234--236","author":"Kulkarni J.","key":"e_1_2_1_13_1","unstructured":"J. Kulkarni , B. Geuskens , T. Karnik , M. Khellah , J. Tschanz , J., and V. De . 2012. Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM . In Proceedings of the IEEE International Solid-State Circuits Conference. 234--236 . J. Kulkarni, B. Geuskens, T. Karnik, M. Khellah, J. Tschanz, J., and V. De. 2012. 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