{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,7]],"date-time":"2026-02-07T04:59:27Z","timestamp":1770440367823,"version":"3.49.0"},"reference-count":35,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2014,11,18]],"date-time":"2014-11-18T00:00:00Z","timestamp":1416268800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Funding Program for World-Leading Innovative R&D on Science and Technology"},{"DOI":"10.13039\/501100001691","name":"Japan Society for the Promotion of Science","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001691","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100002770","name":"Cabinet Office, Government of Japan","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100002770","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2014,11,18]]},"abstract":"<jats:p>\n            Reversible logic has applications in low-power computing and quantum computing. However, there are few existing designs for reversible floating-point adders and none suitable for quantum computation. In this article, we propose a resource-efficient reversible floating-point adder, suitable for binary quantum computation, improving the design of Nachtigal et al. [2011]. Our work focuses on improving the reversible designs of the alignment unit and the normalization unit, which are the most expensive parts. By changing a few elements of the existing algorithm, including the circuit designs of the RLZC (reversible leading zero counter) and converter, we have reduced the cost by about 68%. We also propose quantum designs adapted to use gates from fault-tolerant libraries. The\n            <jats:italic>KQ<\/jats:italic>\n            for our fault-tolerant design is almost 60 times as expensive as for a 32-bit fixed-point addition. We note that the floating-point representation makes in-place, truly reversible arithmetic impossible, requiring us to retain both inputs, which limits the sustainability of its use for quantum computation.\n          <\/jats:p>","DOI":"10.1145\/2629525","type":"journal-article","created":{"date-parts":[[2014,11,18]],"date-time":"2014-11-18T14:21:03Z","timestamp":1416320463000},"page":"1-18","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":12,"title":["A Resource-Efficient Design for a Reversible Floating Point Adder in Quantum Computing"],"prefix":"10.1145","volume":"11","author":[{"given":"Trung Duc","family":"Nguyen","sequence":"first","affiliation":[{"name":"Keio University, Kanagawa, Japan"}]},{"given":"Rodney","family":"Van Meter","sequence":"additional","affiliation":[{"name":"Keio University, Kanagawa, Japan"}]}],"member":"320","published-online":{"date-parts":[[2014,11,18]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"M. 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