{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,18]],"date-time":"2026-04-18T21:43:32Z","timestamp":1776548612926,"version":"3.51.2"},"reference-count":41,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2014,12,30]],"date-time":"2014-12-30T00:00:00Z","timestamp":1419897600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2014,12,30]]},"abstract":"<jats:p>Reversible logic is emerging as a prospective logic design style for implementing ultra-low-power VLSI circuits. It promises low-power consuming circuits by nullifying the energy dissipation in irreversible logic. On the other hand, as a potential alternative to CMOS technology, Quantum-dot Cellular Automata (QCA) promises energy efficient digital design with high device density and high computing speed. The integration of reversible logic in QCA circuit is expected to be effective in addressing the issue of energy dissipation at nano scale regime. This work targets the design of reversible ALU (arithmetic logic unit) in QCA framework and proposes a new \u201cReversible QCA\u201d (RQCA). The primary design focus is on optimizing the number of reversible gates, quantum cost and the garbage outputs that are the most important hindrances in realizing reversible logic. Besides optimization, the fault coverage capability of RQCA under missing\/additional cell deposition defects is analysed. The scope of reversible logic is further outstretched by introducing a novel DFT (design for testability) architecture around the reversible ALU that reduces testing overhead. The performance of proposed ALU is evaluated, subjected to different faults, and is established to be more effective than the existing ALU.<\/jats:p>","DOI":"10.1145\/2629538","type":"journal-article","created":{"date-parts":[[2015,1,5]],"date-time":"2015-01-05T13:27:09Z","timestamp":1420464429000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":43,"title":["Realizing Reversible Computing in QCA Framework Resulting in Efficient Design of Testable ALU"],"prefix":"10.1145","volume":"11","author":[{"given":"Bibhash","family":"Sen","sequence":"first","affiliation":[{"name":"National Institute of Technology Durgapur"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Manojit","family":"Dutta","sequence":"additional","affiliation":[{"name":"National Institute of Technology Durgapur"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Samik","family":"Some","sequence":"additional","affiliation":[{"name":"National Institute of Technology Durgapur"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Biplab K.","family":"Sikdar","sequence":"additional","affiliation":[{"name":"Indian Institute of Engineering and Science and Technology, Shibpur"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2014,12,30]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Snider","author":"Amlani Islamshah","year":"1999","unstructured":"Islamshah Amlani , Alexei O. Orlov , Geza Toth , Gary H. Bernstein , Craig S. Lent , and Gregory L . Snider . 1999 . Digital logic gate using quantum-dot cellular automata. Science 284, 5412, 289--291. Islamshah Amlani, Alexei O. Orlov, Geza Toth, Gary H. Bernstein, Craig S. Lent, and Gregory L. Snider. 1999. Digital logic gate using quantum-dot cellular automata. Science 284, 5412, 289--291."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.176.0525"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2005.83"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1011415529354"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF01857727"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/1356802.1356955"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACRIM.2011.6033020"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.871622"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.858352"},{"key":"e_1_2_1_10_1","volume-title":"IEEE International Symposium on Circuit and Systems.","author":"ISCAS","year":"2004","unstructured":"ISCAS 2004 . IEEE International Symposium on Circuit and Systems. (2004). \u201cQCA: A promising research area for CAS society\u201d. ISCAS 2004. IEEE International Symposium on Circuit and Systems. (2004). \u201cQCA: A promising research area for CAS society\u201d."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.5555\/789098.790873"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICETET.2011.17"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.53.0183"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/4\/1\/004"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1324177.1324180"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.852667"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2005.46"},{"key":"e_1_2_1_18_1","volume-title":"Design of a reversible alu based on novel reversible logic structures. Master's thesis. Department of Computer Science and Engineering","author":"Morrison Matthew Arthur","unstructured":"Matthew Arthur Morrison . 2012. Design of a reversible alu based on novel reversible logic structures. Master's thesis. Department of Computer Science and Engineering , University of South Florida . Matthew Arthur Morrison. 2012. Design of a reversible alu based on novel reversible logic structures. Master's thesis. Department of Computer Science and Engineering, University of South Florida."},{"key":"e_1_2_1_19_1","volume-title":"Techn. Rep. SAND2006-5990","author":"Murphy S. F.","unstructured":"S. F. Murphy , M. Ottavi , M. Frank , and E. DeBenedictis . 2006. On the design of reversible QDCA systems . Techn. Rep. SAND2006-5990 . S. F. Murphy, M. Ottavi, M. Frank, and E. DeBenedictis. 2006. On the design of reversible QDCA systems. Techn. Rep. SAND2006-5990."},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/NANO.2010.5697746"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.976922"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1216396.1216397"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2005.55"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevA.32.3266"},{"key":"e_1_2_1_25_1","volume-title":"Proceedings of the 6th International Symposium on Representations and Methodology of Future Computing Technology. 201--209","author":"Perkowski Marek","year":"2002","unstructured":"Marek Perkowski , Martin Lukac , Pawel Kerntopf , Mikhail Pivtoraiko , Dongsoo Lee , Hyungock Kim , Woong Hwangbo , Jung wook Kim , and Yong Woo Choi . 2002 . A hierarchical approach to computer-aided design of quantum circuits . In Proceedings of the 6th International Symposium on Representations and Methodology of Future Computing Technology. 201--209 . Marek Perkowski, Martin Lukac, Pawel Kerntopf, Mikhail Pivtoraiko, Dongsoo Lee, Hyungock Kim, Woong Hwangbo, Jung wook Kim, and Yong Woo Choi. 2002. A hierarchical approach to computer-aided design of quantum circuits. In Proceedings of the 6th International Symposium on Representations and Methodology of Future Computing Technology. 201--209."},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2011.2104352"},{"key":"e_1_2_1_27_1","first-page":"81","article-title":"Fault tolerant QCA logic design with coupled majority-minority gate","volume":"1","author":"Sen Bibhash","year":"2010","unstructured":"Bibhash Sen , Mamata Dalui , and Biplab K Sikdar . 2010 . Fault tolerant QCA logic design with coupled majority-minority gate . Int. J. Comput. Appl. 1 , 29, 81 -- 87 . DOI: http:\/\/dx.doi.org\/10.5120\/596-645 10.5120\/596-645 Bibhash Sen, Mamata Dalui, and Biplab K Sikdar. 2010. Fault tolerant QCA logic design with coupled majority-minority gate. Int. J. Comput. Appl. 1, 29, 81--87. DOI: http:\/\/dx.doi.org\/10.5120\/596-645","journal-title":"Int. J. Comput. Appl."},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISED.2012.50"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevA.53.2855"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2008.2005408"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICECTECH.2011.5941987"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2004.834169"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2009.2025038"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2209688"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1088\/1751-8113\/43\/38\/382002"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.1421217"},{"key":"#cr-split#-e_1_2_1_37_1.1","unstructured":"Tommaso Toffoli. 1980. Reversible computing. Tech. rep. MIT\/LCS\/TM-151. DOI: http:\/\/dx.doi.org\/10.1007\/3-540-10003-2104 10.1007\/3-540-10003-2104"},{"key":"#cr-split#-e_1_2_1_37_1.2","doi-asserted-by":"crossref","unstructured":"Tommaso Toffoli. 1980. Reversible computing. Tech. rep. MIT\/LCS\/TM-151. DOI: http:\/\/dx.doi.org\/10.1007\/3-540-10003-2104","DOI":"10.21236\/ADA082021"},{"key":"e_1_2_1_38_1","first-page":"339","article-title":"Optimal design of a reversible full adder","volume":"1","author":"Rentergem Yvan Van","year":"2005","unstructured":"Yvan Van Rentergem and Alexis De Vos . 2005 . Optimal design of a reversible full adder . Int J. Unconvent. Comput. 1 , 339 -- 355 . Yvan Van Rentergem and Alexis De Vos. 2005. Optimal design of a reversible full adder. Int J. Unconvent. Comput. 1, 339--355.","journal-title":"Int J. Unconvent. Comput."},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2003.820815"},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2012.2211613"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2629538","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2629538","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T07:01:18Z","timestamp":1750230078000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2629538"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,12,30]]},"references-count":41,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2014,12,30]]}},"alternative-id":["10.1145\/2629538"],"URL":"https:\/\/doi.org\/10.1145\/2629538","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"value":"1550-4832","type":"print"},{"value":"1550-4840","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,12,30]]},"assertion":[{"value":"2013-09-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2014-04-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2014-12-30","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}