{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:17:14Z","timestamp":1763468234661,"version":"3.41.0"},"reference-count":36,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2015,1,21]],"date-time":"2015-01-21T00:00:00Z","timestamp":1421798400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"7th Framework Program of the European Union through the CLERECO Project","award":["611404"],"award-info":[{"award-number":["611404"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2015,1,21]]},"abstract":"<jats:p>NAND flash memories are becoming the predominant technology in the implementation of mass storage systems for both embedded and high-performance applications. However, when considering data and code storage in Non-Volatile Memories (NVMs), such as NAND flash memories, reliability and performance become a serious concern for systems designers. Designing NAND flash-based systems based on worst-case scenarios leads to waste of resources in terms of performance, power consumption, and storage capacity. This is clearly in contrast with the request for runtime reconfigurability, adaptivity, and resource optimization in modern computing systems. There is a clear trend toward supporting differentiated access modes in flash memory controllers, each one setting a differentiated tradeoff point in the performance-reliability optimization space. This is supported by the possibility of tuning the NAND flash memory performance, reliability, and power consumption through several tuning knobs such as the flash programming algorithm and the flash error correcting code. However, to successfully exploit these degrees of freedom, it is mandatory to clearly understand the effect that the combined tuning of these parameters has on the full NVM subsystem. This article performs a comprehensive quantitative analysis of the benefits provided by the runtime reconfigurability of an MLC NAND flash controller through the combined effect of an adaptable memory programming circuitry coupled with runtime adaptation of the ECC correction capability. The full NVM subsystem is taken into account, starting from a characterization of the low-level circuitry to the effect of the adaptation on a wide set of realistic benchmarks in order to provide readers a clear view of the benefit this combined adaptation may provide at the system level.<\/jats:p>","DOI":"10.1145\/2629562","type":"journal-article","created":{"date-parts":[[2015,1,28]],"date-time":"2015-01-28T14:05:51Z","timestamp":1422453951000},"page":"1-24","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":12,"title":["Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers"],"prefix":"10.1145","volume":"14","author":[{"given":"Davide","family":"Bertozzi","sequence":"first","affiliation":[{"name":"Universit\u00e0 di Ferrara, Ferrara, Italy"}]},{"given":"Stefano Di","family":"Carlo","sequence":"additional","affiliation":[{"name":"Politecnico di Torino, Torino, Italy"}]},{"given":"Salvatore","family":"Galfano","sequence":"additional","affiliation":[{"name":"Politecnico di Torino, Torino, Italy"}]},{"given":"Marco","family":"Indaco","sequence":"additional","affiliation":[{"name":"Politecnico di Torino, Torino, Italy"}]},{"given":"Piero","family":"Olivo","sequence":"additional","affiliation":[{"name":"Universit\u00e0 di Ferrara, Ferrara, Italy"}]},{"given":"Paolo","family":"Prinetto","sequence":"additional","affiliation":[{"name":"Politecnico di Torino, Torino, Italy"}]},{"given":"Cristian","family":"Zambelli","sequence":"additional","affiliation":[{"name":"Universit\u00e0 di Ferrara, Ferrara, Italy"}]}],"member":"320","published-online":{"date-parts":[[2015,1,21]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"G. Atwood A. Fazio D. Mills and B. Reaves. 1997. Intel strataflash memory technology overview. Intel Technology Journal Quarterly 4 (1997). Retrieved from https:\/\/noggin.intel.com\/content\/intel-strataflash- memory-technology-overview.  G. Atwood A. Fazio D. Mills and B. Reaves. 1997. Intel strataflash memory technology overview. Intel Technology Journal Quarterly 4 (1997). Retrieved from https:\/\/noggin.intel.com\/content\/intel-strataflash- memory-technology-overview."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2003.811702"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1016\/S0019-9958(60)90287-4"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/2073460"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2009.24"},{"key":"e_1_2_1_6_1","unstructured":"CMP. 2012. CMP Project. Retrieved from http:\/\/cmp.imag.fr\/.  CMP. 2012. CMP Project. Retrieved from http:\/\/cmp.imag.fr\/."},{"key":"e_1_2_1_7_1","unstructured":"J. Cooke. 2007. The inconvenient truths of NAND flash memory. Flash Memory Summit. Retrieved from http:\/\/download.micron.com\/pdf\/presentations\/events\/flash_mem_summit_jcooke_inconvenient_truths_ nand.pdf.  J. Cooke. 2007. The inconvenient truths of NAND flash memory. Flash Memory Summit. Retrieved from http:\/\/download.micron.com\/pdf\/presentations\/events\/flash_mem_summit_jcooke_inconvenient_truths_ nand.pdf."},{"key":"e_1_2_1_8_1","unstructured":"R. Dan and R. Singer. 2003. Implementing MLC NAND flash for cost-effective high-capacity memory. M-Syst. White paper. Retrieved from http:\/\/tinyurl.com\/o2443mh.  R. Dan and R. Singer. 2003. Implementing MLC NAND flash for cost-effective high-capacity memory. M-Syst. White paper. Retrieved from http:\/\/tinyurl.com\/o2443mh."},{"key":"e_1_2_1_9_1","first-page":"3","article-title":"Design Issues and Challenges of File Systems for Flash Memories. InTech, Croatia","volume":"1","author":"Carlo S. Di","year":"2011","unstructured":"S. Di Carlo , M. Fabiano , P. Prinetto , and M. Caramia . 2011 . Design Issues and Challenges of File Systems for Flash Memories. InTech, Croatia , Chapter 1 , 3 -- 30 . S. Di Carlo, M. Fabiano, P. Prinetto, and M. Caramia. 2011. Design Issues and Challenges of File Systems for Flash Memories. InTech, Croatia, Chapter 1, 3--30.","journal-title":"Chapter"},{"key":"e_1_2_1_10_1","unstructured":"Evatronix. 2012. Evatronix NANDFLASH-CTRL NAND Flash Memory Controller. Retrieved from http:\/\/www.evatronix.pl\/products\/docs.html&quest;id=10&product=TkFOREZMQVNILUN UUkw=.  Evatronix. 2012. Evatronix NANDFLASH-CTRL NAND Flash Memory Controller. Retrieved from http:\/\/www.evatronix.pl\/products\/docs.html&quest;id=10&product=TkFOREZMQVNILUN UUkw=."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2013.03.002"},{"key":"e_1_2_1_12_1","unstructured":"E. Grochowski and R. E. Fontana. 2012. Future technology challenges for NAND flash and HDD products. Flash Memory Summit. Retrieved from http:\/\/www.flashmemorysummit.com\/English\/Collaterals\/Proceedings\/2012\/20120821_S102A_Grochowski.pdf.  E. Grochowski and R. E. Fontana. 2012. Future technology challenges for NAND flash and HDD products. Flash Memory Summit. Retrieved from http:\/\/www.flashmemorysummit.com\/English\/Collaterals\/Proceedings\/2012\/20120821_S102A_Grochowski.pdf."},{"volume-title":"Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA\u201911)","author":"Henkel J.","key":"e_1_2_1_13_1","unstructured":"J. Henkel , L. Bauer , M. H\u00fcbner , and A. Grudnitsky . 2011. i-Core: A run-time adaptive processor for embedded multi-core systems . In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA\u201911) . ERSA-ADN. J. Henkel, L. Bauer, M. H\u00fcbner, and A. Grudnitsky. 2011. i-Core: A run-time adaptive processor for embedded multi-core systems. In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA\u201911). ERSA-ADN."},{"key":"e_1_2_1_14_1","unstructured":"iozone.org. 2012. IOzone File System Benchmark. Retrieved from http:\/\/www.iozone.org.  iozone.org. 2012. IOzone File System Benchmark. Retrieved from http:\/\/www.iozone.org."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2007.909984"},{"key":"e_1_2_1_16_1","unstructured":"JEDEC Solid State Technology Association. 2011. Failure mechanisms and models for semiconductor devices (JEP122G). Retrieved from http:\/\/www.jedec.org\/standards-documents\/docs\/jep-122e.  JEDEC Solid State Technology Association. 2011. Failure mechanisms and models for semiconductor devices (JEP122G). Retrieved from http:\/\/www.jedec.org\/standards-documents\/docs\/jep-122e."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.914327"},{"key":"e_1_2_1_19_1","first-page":"12","article-title":"Data retention characteristics of sub-100 nm NAND flash memory cells","volume":"24","author":"Lee J. D.","year":"2003","unstructured":"J. D. Lee , J. H. Choi , D. Park , and K. Kim . 2003 . Data retention characteristics of sub-100 nm NAND flash memory cells . IEEE Electron Device Letters 24 , 12 (Dec. 2003), 748--750. J. D. Lee, J. H. Choi, D. Park, and K. Kim. 2003. Data retention characteristics of sub-100 nm NAND flash memory cells. IEEE Electron Device Letters 24, 12 (Dec. 2003), 748--750.","journal-title":"IEEE Electron Device Letters"},{"volume-title":"Proceedings of the 10th USENIX Conference on File and Storage Technologies (FAST\u201912)","author":"Liu R.-S.","key":"e_1_2_1_20_1","unstructured":"R.-S. Liu , C.-L. Yang , and W. Wu . 2012. Optimizing NAND flash-based SSDs via retention relaxation . In Proceedings of the 10th USENIX Conference on File and Storage Technologies (FAST\u201912) . USENIX Association. Retrieved from http:\/\/static.usenix.org\/event\/fast12\/tech\/full_papers\/Liu.pdf. R.-S. Liu, C.-L. Yang, and W. Wu. 2012. Optimizing NAND flash-based SSDs via retention relaxation. In Proceedings of the 10th USENIX Conference on File and Storage Technologies (FAST\u201912). USENIX Association. Retrieved from http:\/\/static.usenix.org\/event\/fast12\/tech\/full_papers\/Liu.pdf."},{"key":"e_1_2_1_21_1","first-page":"1","article-title":"Investigation of the programming accuracy of a double-verify ISPP algorithm for nanoscale NAND Flash memories. In Proceedings of the IEEE International Reliability Physics Symposium (IRPS\u201911). IEEE","volume":"5","author":"Miccoli C.","year":"2011","unstructured":"C. Miccoli , C. Monzio Compagnoni , A. S. Spinelli , and A. L. Lacaita . 2011 . Investigation of the programming accuracy of a double-verify ISPP algorithm for nanoscale NAND Flash memories. In Proceedings of the IEEE International Reliability Physics Symposium (IRPS\u201911). IEEE , MY. 5 . 1 --MY.5.6. C. Miccoli, C. Monzio Compagnoni, A. S. Spinelli, and A. L. Lacaita. 2011. Investigation of the programming accuracy of a double-verify ISPP algorithm for nanoscale NAND Flash memories. In Proceedings of the IEEE International Reliability Physics Symposium (IRPS\u201911). IEEE, MY.5.1--MY.5.6.","journal-title":"MY."},{"key":"e_1_2_1_22_1","doi-asserted-by":"crossref","unstructured":"R. Micheloni L. Crippa and A. Marelli. 2010. Inside NAND Flash Memories. Springer-Verlag Berlin.  R. Micheloni L. Crippa and A. Marelli. 2010. Inside NAND Flash Memories. Springer-Verlag Berlin.","DOI":"10.1007\/978-90-481-9431-5"},{"key":"e_1_2_1_23_1","doi-asserted-by":"crossref","unstructured":"R. Micheloni A. Marelli and K. Eshghi. 2013. Inside Solid State Drives (SSDs). Springer Berlin.   R. Micheloni A. Marelli and K. Eshghi. 2013. Inside Solid State Drives (SSDs). Springer Berlin.","DOI":"10.1007\/978-94-007-5146-0"},{"volume-title":"Proceedings of the IEEE International Reliability Physics Symposium (IRPS\u201908)","author":"Mielke N.","key":"e_1_2_1_24_1","unstructured":"N. Mielke , T. Marquart , N. Wu , J. Kessenich , H. Belgal , E. Schares , F. Trivedi , E. Goodness , and L. R. Nevill . 2008. Bit error rate in NAND Flash memories . In Proceedings of the IEEE International Reliability Physics Symposium (IRPS\u201908) . IEEE, 9--19. N. Mielke, T. Marquart, N. Wu, J. Kessenich, H. Belgal, E. Schares, F. Trivedi, E. Goodness, and L. R. Nevill. 2008. Bit error rate in NAND Flash memories. In Proceedings of the IEEE International Reliability Physics Symposium (IRPS\u201908). IEEE, 9--19."},{"volume-title":"Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 502--507","author":"Mohan V.","key":"e_1_2_1_25_1","unstructured":"V. Mohan , S. Gurumurthi , and M. R. Stan . 2010. FlashPower: A detailed power model for NAND flash memory . In Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 502--507 . V. Mohan, S. Gurumurthi, and M. R. Stan. 2010. FlashPower: A detailed power model for NAND flash memory. In Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 502--507."},{"key":"e_1_2_1_26_1","unstructured":"ONFI Workgroup. 2012. Open NAND Flash Interface. Retrieved from http:\/\/onfi.org.  ONFI Workgroup. 2012. Open NAND Flash Interface. Retrieved from http:\/\/onfi.org."},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/2541940.2541959"},{"volume-title":"Proceedings of the 9th USENIX Conference on File and Storage Technologies (FAST\u201911)","author":"Pan Y.","key":"e_1_2_1_28_1","unstructured":"Y. Pan , G. Dong , and T. Zhang . 2011. Exploiting memory device wear-out dynamics to improve NAND flash memory system performance . In Proceedings of the 9th USENIX Conference on File and Storage Technologies (FAST\u201911) . USENIX Association, Berkeley, CA. Y. Pan, G. Dong, and T. Zhang. 2011. Exploiting memory device wear-out dynamics to improve NAND flash memory system performance. In Proceedings of the 9th USENIX Conference on File and Storage Technologies (FAST\u201911). USENIX Association, Berkeley, CA."},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540712"},{"key":"e_1_2_1_30_1","unstructured":"Samsung. 2012. Samsung KFG4GH6x4M 4Gb Flex-OneNAND M-die Datasheet.  Samsung. 2012. Samsung KFG4GH6x4M 4Gb Flex-OneNAND M-die Datasheet."},{"volume-title":"IEEE International Reliability Physics Symposium (IRPS\u201910)","author":"Spessot A.","key":"e_1_2_1_31_1","unstructured":"A. Spessot , A. Calderoni , P. Fantini , A. S. Spinelli , C. M Compagnoni , F. Farina , A. L. Lacaita , and A. Marmiroli . 2010. Variability effects on the VT distribution of nanoscale NAND flash memories . In IEEE International Reliability Physics Symposium (IRPS\u201910) . IEEE, 970--974. A. Spessot, A. Calderoni, P. Fantini, A. S. Spinelli, C. M Compagnoni, F. Farina, A. L. Lacaita, and A. Marmiroli. 2010. Variability effects on the VT distribution of nanoscale NAND flash memories. In IEEE International Reliability Physics Symposium (IRPS\u201910). IEEE, 970--974."},{"key":"e_1_2_1_32_1","unstructured":"Standard Performance Evaluation Corporation. 2013. SPEC Benchmarks. Retrieved from http:\/\/www.spec.org.  Standard Performance Evaluation Corporation. 2013. SPEC Benchmarks. Retrieved from http:\/\/www.spec.org."},{"key":"e_1_2_1_33_1","volume-title":"Proceedings 7th IEEE International Workshop on Storage Network Architecture and Parallel I\/O (SNAPI\u201911)","author":"Sun H.","year":"2011","unstructured":"H. Sun , B. Wood , and P. Grayson . 2011. Qualifying reliability of solid-state storage from multiple aspects . In Proceedings 7th IEEE International Workshop on Storage Network Architecture and Parallel I\/O (SNAPI\u201911) . IEEE. Retrieved from http:\/\/storageconference.org\/ 2011 \/Papers\/SNAPI\/1.Sun.pdf. H. Sun, B. Wood, and P. Grayson. 2011. Qualifying reliability of solid-state storage from multiple aspects. In Proceedings 7th IEEE International Workshop on Storage Network Architecture and Parallel I\/O (SNAPI\u201911). IEEE. Retrieved from http:\/\/storageconference.org\/2011\/Papers\/SNAPI\/1.Sun.pdf."},{"key":"e_1_2_1_34_1","volume-title":"Proceedings of the 6th USENIX Conference on File and Storage Technologies (FAST\u201908)","author":"Wilson A.","year":"2008","unstructured":"A. Wilson . 2008 . The new and improved filebench . In Proceedings of the 6th USENIX Conference on File and Storage Technologies (FAST\u201908) . USENIX, Retrieved from https:\/\/www.usenix.org\/legacy\/events\/fast08\/wips_posters\/wilson-wip.pdf. A. Wilson. 2008. The new and improved filebench. In Proceedings of the 6th USENIX Conference on File and Storage Technologies (FAST\u201908). USENIX, Retrieved from https:\/\/www.usenix.org\/legacy\/events\/fast08\/wips_posters\/wilson-wip.pdf."},{"key":"e_1_2_1_35_1","unstructured":"E. Yaakobi J. Ma A. Caulfield L. Grupp S. Swanson P. H. Siegel and J. K. Wolf. 2009. Error correction coding for flash memories. Flash Memory Summit. Retrieved from http:\/\/www.bswd.com\/FMS09\/FMS09-201-Yaakobi.pdf.  E. Yaakobi J. Ma A. Caulfield L. Grupp S. Swanson P. H. Siegel and J. K. Wolf. 2009. Error correction coding for flash memories. Flash Memory Summit. Retrieved from http:\/\/www.bswd.com\/FMS09\/FMS09-201-Yaakobi.pdf."},{"key":"e_1_2_1_36_1","volume-title":"Proceedings of the IEEE GLOBECOM Workshops (GC Wkshps\u201910)","author":"Yaakobi E.","year":"1856","unstructured":"E. Yaakobi , J. Ma , L. Grupp , P. H. Siegel , S. Swanson , and J. K. Wolf . 2010. Error characterization and coding schemes for flash memories . In Proceedings of the IEEE GLOBECOM Workshops (GC Wkshps\u201910) . IEEE, 1856 --1860. E. Yaakobi, J. Ma, L. Grupp, P. H. Siegel, S. Swanson, and J. K. Wolf. 2010. Error characterization and coding schemes for flash memories. In Proceedings of the IEEE GLOBECOM Workshops (GC Wkshps\u201910). IEEE, 1856--1860."},{"volume-title":"Proceedings of Design, Automation Test in Europe Conference Exhibition (DATE\u201912)","author":"Zambelli C.","key":"e_1_2_1_37_1","unstructured":"C. Zambelli , M. Indaco , M. Fabiano , S. Di Carlo , P. Prinetto , P. Olivo , and D. Bertozzi . 2012. A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories . In Proceedings of Design, Automation Test in Europe Conference Exhibition (DATE\u201912) . IEEE, 881--886. C. Zambelli, M. Indaco, M. Fabiano, S. Di Carlo, P. Prinetto, P. Olivo, and D. Bertozzi. 2012. A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories. In Proceedings of Design, Automation Test in Europe Conference Exhibition (DATE\u201912). IEEE, 881--886."}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2629562","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2629562","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T06:13:29Z","timestamp":1750227209000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2629562"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,1,21]]},"references-count":36,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2015,1,21]]}},"alternative-id":["10.1145\/2629562"],"URL":"https:\/\/doi.org\/10.1145\/2629562","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"type":"print","value":"1539-9087"},{"type":"electronic","value":"1558-3465"}],"subject":[],"published":{"date-parts":[[2015,1,21]]},"assertion":[{"value":"2013-10-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2014-04-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2015-01-21","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}