{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,26]],"date-time":"2026-02-26T15:32:46Z","timestamp":1772119966488,"version":"3.50.1"},"reference-count":25,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2015,3,24]],"date-time":"2015-03-24T00:00:00Z","timestamp":1427155200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Enterprise Computing Center"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2015,4,17]]},"abstract":"<jats:p>FPGA-based data processing is becoming increasingly relevant in data centers, as the transformation of existing applications into dataflow architectures can bring significant throughput and power benefits. Furthermore, a tighter integration of computing and network is appealing, as it overcomes traditional bottlenecks between CPUs and network interfaces, and dramatically reduces latency.<\/jats:p>\n          <jats:p>In this article, we present the design of a novel hash table, a fundamental building block used in many applications, to enable data processing on FPGAs close to the network. We present a fully pipelined design capable of sustaining consistent 10Gbps line-rate processing by deploying a concurrent mechanism to handle hash collisions. We address additional design challenges such as support for a broad range of key sizes without stalling the pipeline through careful matching of lookup time with packet reception time. Finally, the design is based on a scalable architecture that can be easily parameterized to work with different memory types operating at different access speeds and latencies.<\/jats:p>\n          <jats:p>We have tested the proposed hash table in an FPGA-based memcached appliance implementing a main-memory key-value store in hardware. The hash table is used to index 2 million entries in 24GB of external DDR3 DRAM while sustaining 13 million requests per second, the maximum packet rate that can be achieved with UDP packets on a 10Gbps link for this application.<\/jats:p>","DOI":"10.1145\/2629582","type":"journal-article","created":{"date-parts":[[2015,3,25]],"date-time":"2015-03-25T16:03:43Z","timestamp":1427299423000},"page":"1-15","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":25,"title":["A Hash Table for Line-Rate Data Processing"],"prefix":"10.1145","volume":"8","author":[{"given":"Zsolt","family":"Istv\u00e1n","sequence":"first","affiliation":[{"name":"Systems Group, Department of Computer Science, ETH Z\u00fcrich, Switzerland"}]},{"given":"Gustavo","family":"Alonso","sequence":"additional","affiliation":[{"name":"Systems Group, Department of Computer Science, ETH Z\u00fcrich, Switzerland"}]},{"given":"Michaela","family":"Blott","sequence":"additional","affiliation":[{"name":"Xilinx Labs, Citywest Business Campus, Dublin, Ireland"}]},{"given":"Kees","family":"Vissers","sequence":"additional","affiliation":[{"name":"Xilinx Labs, San Jose, California, United States"}]}],"member":"320","published-online":{"date-parts":[[2015,3,24]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Proceedings of the 6th Conference on Innovative Data Systems Research (CIDR).","author":"Arasu Arvind","year":"2013","unstructured":"Arvind Arasu , Spyros Blanas , Ken Eguro , Raghav Kaushik , Donald Kossmann , Ravi Ramamurthy , and Ramaratnam Venkatesan . 2013 . Orthogonal security with Cipherbase . In Proceedings of the 6th Conference on Innovative Data Systems Research (CIDR). Arvind Arasu, Spyros Blanas, Ken Eguro, Raghav Kaushik, Donald Kossmann, Ravi Ramamurthy, and Ramaratnam Venkatesan. 2013. Orthogonal security with Cipherbase. In Proceedings of the 6th Conference on Innovative Data Systems Research (CIDR)."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2254756.2254766"},{"key":"e_1_2_1_3_1","volume-title":"Proceedings of the International Conference on High Performance Switching and Routing. IEEE","author":"Bando Masanori","unstructured":"Masanori Bando , N. Sertac Artan , and H. Jonathan Chao . 2009. Flashlook: 100-Gbps hash-tuned route lookup architecture . In Proceedings of the International Conference on High Performance Switching and Routing. IEEE , Los Alamitos, CA, 1--8. Masanori Bando, N. Sertac Artan, and H. Jonathan Chao. 2009. Flashlook: 100-Gbps hash-tuned route lookup architecture. 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Retrieved March 2, 2015 , from http:\/\/www.conveycomputer.com\/files\/6113\/7998\/5068\/CONV-13-047&lowbar;MCD&lowbar;whit epaper.pdf. Convey. 2013. Ramping Up Web Server Memcached Capabilities with Hybrid-Core Computing. White Paper. Retrieved March 2, 2015, from http:\/\/www.conveycomputer.com\/files\/6113\/7998\/5068\/CONV-13-047&lowbar;MCD&lowbar;whit epaper.pdf."},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2013.38"},{"key":"e_1_2_1_10_1","article-title":"Distributed caching with memcached","volume":"2004","author":"Fitzpatrick Brad","year":"2004","unstructured":"Brad Fitzpatrick . 2004 . Distributed caching with memcached . Linux Journal 2004 , 124, 72--74. Brad Fitzpatrick. 2004. Distributed caching with memcached. Linux Journal 2004, 124, 72--74.","journal-title":"Linux Journal"},{"key":"e_1_2_1_11_1","unstructured":"Phil Francisco. 2011. The Netezza data appliance architecture: A platform for high performance data warehousing and analytics. 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