{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,7]],"date-time":"2026-01-07T23:04:10Z","timestamp":1767827050727,"version":"3.49.0"},"reference-count":31,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2014,7,31]],"date-time":"2014-07-31T00:00:00Z","timestamp":1406764800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2014,10,27]]},"abstract":"<jats:p>Leakage energy is a growing concern in current and future microprocessors. Functional units of microprocessors are responsible for a major fraction of this energy. Therefore, reducing functional unit leakage has received much attention in recent years. Power gating is one of the most widely used techniques to minimize leakage energy. Power gating turns off the functional units during the idle periods to reduce the leakage. Therefore, the amount of leakage energy savings is directly proportional to the idle time duration. This article focuses on increasing the idle interval for the higher SIMD lanes. The applications are profiled dynamically, in a hardware\/software codesigned environment, to find the higher SIMD lanes' usage pattern. If the higher lanes need to be turned on for small time periods, the corresponding portion of the code is devectorized to keep the higher lanes off. The devectorized code is executed on the lowest SIMD lane. Our experimental results show that the average energy savings of the proposed mechanism are 15%, 12%, and 71% greater than power gating for SPECFP2006, Physicsbench, and Eigen benchmark suites, respectively. Moreover, the slowdown caused by devectorization is negligible.<\/jats:p>","DOI":"10.1145\/2629681","type":"journal-article","created":{"date-parts":[[2014,8,1]],"date-time":"2014-08-01T20:13:24Z","timestamp":1406924004000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":11,"title":["Efficient Power Gating of SIMD Accelerators Through Dynamic Selective Devectorization in an HW\/SW Codesigned Environment"],"prefix":"10.1145","volume":"11","author":[{"given":"Rakesh","family":"Kumar","sequence":"first","affiliation":[{"name":"Universitat Polit\u00e8cnica De Catalunya, Barcelona, Spain"}]},{"given":"Alejandro","family":"Mart\u00ednez","sequence":"additional","affiliation":[{"name":"Intel Barcelona Research Center, Intel Labs, Barcelona, Spain"}]},{"given":"Antonio","family":"Gonz\u00e1lez","sequence":"additional","affiliation":[{"name":"Intel Barcelona Research Center, Intel Labs -- UPC, Barcelona, Spain"}]}],"member":"320","published-online":{"date-parts":[[2014,7,31]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.102"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1013235.1013244"},{"key":"e_1_2_1_3_1","first-page":"1","article-title":"Cortex-A8: High speed, low power","volume":"11","author":"Baron M.","year":"2005","unstructured":"M. Baron . 2005 . Cortex-A8: High speed, low power . Microprocessor Report 11 , 14, 1 -- 6 . M. Baron. 2005. Cortex-A8: High speed, low power. Microprocessor Report 11, 14, 1--6.","journal-title":"Microprocessor Report"},{"key":"e_1_2_1_4_1","volume-title":"Proceedings of the 4th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies.","author":"Bira Calin","year":"2013","unstructured":"Calin Bira , Liviu Gugu , Radu Hobincu , Valeriu Codreanu , Lucian Petrica , and Sorin Cotofana . 2013 . An energy effective SIMD accelerator for visual pattern matching . In Proceedings of the 4th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. Calin Bira, Liviu Gugu, Radu Hobincu, Valeriu Codreanu, Lucian Petrica, and Sorin Cotofana. 2013. An energy effective SIMD accelerator for visual pattern matching. In Proceedings of the 4th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2581122.2544142"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/776261.776263"},{"key":"e_1_2_1_7_1","volume-title":"Wireless Symposium. Motorola","author":"D'Arcy Paul","year":"1999","unstructured":"Paul D'Arcy and Scott Beach . 1999 . StarCore SC140: A new DSP architecture for portable devices . In Wireless Symposium. Motorola , September 1999. Paul D'Arcy and Scott Beach. 1999. StarCore SC140: A new DSP architecture for portable devices. In Wireless Symposium. Motorola, September 1999."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.848475"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/264107.264126"},{"key":"e_1_2_1_10_1","volume-title":"EIGEN is a C&plus;&plus","unstructured":"Eigen. 2014. EIGEN is a C&plus;&plus ; Template Library for Linear Algebra : Matrices, Vectors , Numerical Solvers, and Related Algorithms. Retrieved from http:\/\/eigen.tuxfamily.org\/index.php&quest;title=Main_Page. Eigen. 2014. EIGEN is a C&plus;&plus; Template Library for Linear Algebra: Matrices, Vectors, Numerical Solvers, and Related Algorithms. Retrieved from http:\/\/eigen.tuxfamily.org\/index.php&quest;title=Main_Page."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1013235.1013249"},{"key":"e_1_2_1_12_1","volume-title":"Intel\u00ae 64 and IA-32 Architectures Software Developer's Manual","author":"Intel Corporation","unstructured":"Intel Corporation . 2011. Intel\u00ae 64 and IA-32 Architectures Software Developer's Manual , Volume 1-- 3 . Retrieved from http:\/\/www.intel.com\/content\/www\/us\/en\/processors\/architectures-software-developer-manuals.html&quest;iid=tech_vt_tech&plus;64--32_manuals. Intel Corporation. 2011. Intel\u00ae 64 and IA-32 Architectures Software Developer's Manual, Volume 1--3. Retrieved from http:\/\/www.intel.com\/content\/www\/us\/en\/processors\/architectures-software-developer-manuals.html&quest;iid=tech_vt_tech&plus;64--32_manuals."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/1148882.1148891"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2012429"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PAD.2013.10"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.526925"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065034"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1594233.1594331"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/2541940.2541978"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736026"},{"key":"e_1_2_1_22_1","volume-title":"Proceedings of the 4th Workshop on Architectural and Microarchitectural Support for Binary Translation (AMAS-BT'11)","author":"Pavlou Demos","year":"2011","unstructured":"Demos Pavlou , Aleksandar Brankovic , Rakesh Kumar , Maria Gregori , Kyriakos Stavrou , Enric Gibert , and Antonio Gonzalez . 2011 . DARCO: Infrastructure for research on HW\/SW co-designed virtual machines . In Proceedings of the 4th Workshop on Architectural and Microarchitectural Support for Binary Translation (AMAS-BT'11) , Held in Conjuction with the 38th International Symposium on Computer Architecture (ISCA-38). Demos Pavlou, Aleksandar Brankovic, Rakesh Kumar, Maria Gregori, Kyriakos Stavrou, Enric Gibert, and Antonio Gonzalez. 2011. DARCO: Infrastructure for research on HW\/SW co-designed virtual machines. In Proceedings of the 4th Workshop on Architectural and Microarchitectural Support for Binary Translation (AMAS-BT'11), Held in Conjuction with the 38th International Symposium on Computer Architecture (ISCA-38)."},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2151024.2151046"},{"key":"e_1_2_1_24_1","volume-title":"Proceedings of the 1999 Workshop on Binary Translation, IEEE Computer Society Technical Committee on Computer Architecture Newsletter. 2--11","author":"Sathaye Sumedh","year":"1999","unstructured":"Sumedh Sathaye , Paul Ledak , Jay Leblanc , Stephen Kosonocky , Michael Gschwind , Jason Fritts , Arthur Bright , Erik Altman , and Craig Agricola . 1999 . BOA: Targeting multi-gigahertz with binary translation . In Proceedings of the 1999 Workshop on Binary Translation, IEEE Computer Society Technical Committee on Computer Architecture Newsletter. 2--11 . Sumedh Sathaye, Paul Ledak, Jay Leblanc, Stephen Kosonocky, Michael Gschwind, Jason Fritts, Arthur Bright, Erik Altman, and Craig Agricola. 1999. BOA: Targeting multi-gigahertz with binary translation. In Proceedings of the 1999 Workshop on Binary Translation, IEEE Computer Society Technical Committee on Computer Architecture Newsletter. 2--11."},{"key":"e_1_2_1_25_1","unstructured":"Manu Sporny Gray Carper and Jonathan Turner. 2002. The PlaysStation 2 Linux Kit Handbook. Retrieved from http:\/\/ps2linux.no-ip.info\/playstation2-linux.com\/download\/p2lsd\/p2lkit-handbook.html.  Manu Sporny Gray Carper and Jonathan Turner. 2002. The PlaysStation 2 Linux Kit Handbook. Retrieved from http:\/\/ps2linux.no-ip.info\/playstation2-linux.com\/download\/p2lsd\/p2lkit-handbook.html."},{"key":"e_1_2_1_26_1","volume-title":"SPEC CPU2006 Benchmarks.","author":"Standard Performance Evaluation Corporation","year":"2014","unstructured":"Standard Performance Evaluation Corporation . 2014 . SPEC CPU2006 Benchmarks. Retrieved from http:\/\/www.spec.org\/cpu2006\/. Standard Performance Evaluation Corporation. 2014. SPEC CPU2006 Benchmarks. Retrieved from http:\/\/www.spec.org\/cpu2006\/."},{"key":"e_1_2_1_27_1","volume-title":"Dynamic sleep transistor and body bias for active leakage power control of microprocessors","author":"Tschanz James W.","year":"1838","unstructured":"James W. Tschanz , Siva G. Narendra , Yibin Ye , Bradley A. Bloechel , Shekhar Borkar , and Vivek De . Dynamic sleep transistor and body bias for active leakage power control of microprocessors . IEEE Journal of Solid-State Circuits , 38, 11, 1838 --1845. James W. Tschanz, Siva G. Narendra, Yibin Ye, Bradley A. Bloechel, Shekhar Borkar, and Vivek De. Dynamic sleep transistor and body bias for active leakage power control of microprocessors. IEEE Journal of Solid-State Circuits, 38, 11, 1838--1845."},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2013.6494980"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.1998.687996"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250691"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.22"}],"container-title":["ACM Transactions on Architecture and Code Optimization"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2629681","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2629681","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T06:13:30Z","timestamp":1750227210000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2629681"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,7,31]]},"references-count":31,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2014,10,27]]}},"alternative-id":["10.1145\/2629681"],"URL":"https:\/\/doi.org\/10.1145\/2629681","relation":{},"ISSN":["1544-3566","1544-3973"],"issn-type":[{"value":"1544-3566","type":"print"},{"value":"1544-3973","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,7,31]]},"assertion":[{"value":"2013-06-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2014-04-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2014-07-31","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}