{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,21]],"date-time":"2026-05-21T02:59:48Z","timestamp":1779332388387,"version":"3.51.4"},"reference-count":38,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2015,1,21]],"date-time":"2015-01-21T00:00:00Z","timestamp":1421798400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"crossref","id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2015,1,21]]},"abstract":"<jats:p>Device reliability and manufacturability have emerged as dominant concerns in end-of-road CMOS devices. An increasing number of hardware failures are attributed to manufacturability or reliability problems. Maintaining an acceptable manufacturing yield for chips containing tens of billions of transistors with wide variations in device parameters has been identified as a great challenge. Additionally, today\u2019s nanometer scale devices suffer from accelerated aging effects because of the extreme operating temperature and electric fields they are subjected to. Unless addressed in design, aging-related defects can significantly reduce the lifetime of a product. In this article, we investigate a micro-architectural scheme for improving yield and reliability of homogeneous chip multiprocessors (CMPs). The proposed solution involves a hardware framework that enables us to utilize the redundancies inherent in a multicore system to keep the system operational in the face of partial failures. A micro-architectural modification allows a faulty core in a CMP to use another core\u2019s resources to service any instruction that the former cannot execute correctly by itself. This service improves yield and reliability but may cause loss of performance. The target platform for quantitative evaluation of performance under degradation is a dual-core and a quad-core chip multiprocessor with one or more cores sustaining partial failure. Simulation studies indicate that when a large, high-latency, and sparingly used unit such as a floating-point unit fails in a core, correct execution may be sustained through outsourcing with at most a 16% impact on performance for a floating-point intensive application. For applications with moderate floating-point load, the degradation is insignificant. The performance impact may be mitigated even further by judicious selection of the cores to commandeer depending on the current load on each of the candidate cores. The area overhead is also negligible due to resource reuse.<\/jats:p>","DOI":"10.1145\/2629688","type":"journal-article","created":{"date-parts":[[2015,1,28]],"date-time":"2015-01-28T14:05:51Z","timestamp":1422453951000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["A Hardware Framework for Yield and Reliability Enhancement in Chip Multiprocessors"],"prefix":"10.1145","volume":"14","author":[{"given":"Abhisek","family":"Pan","sequence":"first","affiliation":[{"name":"Purdue University, West Lafayette, IN"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rance","family":"Rodrigues","sequence":"additional","affiliation":[{"name":"University of Massachusetts, Amherst, Beaverton OR"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sandip","family":"Kundu","sequence":"additional","affiliation":[{"name":"University of Massachusetts, Amherst, MA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,1,21]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2009.118"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.5555\/320080.320111"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.110"},{"key":"e_1_2_1_4_1","volume-title":"Proceedings of the 2011 International Conference on Embedded Computer Systems (SAMOS\u201911)","author":"Borodin D.","year":"2011"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.461.0077"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/1009382.1009721"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2005.8"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339657"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1077603.1077657"},{"key":"e_1_2_1_10_1","volume-title":"CASH: Revisiting hardware sharing in single-chip parallel processor. IRISA Report","author":"Dolbeau R.","year":"2002"},{"key":"e_1_2_1_11_1","volume-title":"Proceedings of the 14th IEEE Symposium on Computer Arithmetic. 266--273","author":"Gerwig G.","year":"1999"},{"key":"e_1_2_1_12_1","volume-title":"Automation Test in Europe Conference Exhibition (DATE)","author":"Gizopoulos D.","year":"2011"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771786"},{"key":"e_1_2_1_14_1","unstructured":"ITRS. 2012. The International Technology Roadmap for Semiconductors Reports. http:\/\/public.itrs.net\/reports.html (2012).  ITRS. 2012. The International Technology Roadmap for Semiconductors Reports. http:\/\/public.itrs.net\/reports.html (2012)."},{"key":"e_1_2_1_15_1","doi-asserted-by":"crossref","unstructured":"N. K. Jha and S. Gupta. 2003. Testing of Digital Systems. Cambridge University Press.   N. K. Jha and S. Gupta. 2003. Testing of Digital Systems. Cambridge University Press.","DOI":"10.1017\/CBO9780511816321"},{"key":"e_1_2_1_16_1","volume-title":"Proceedings of the 2nd Workshop on High Performance Computing Reliability Issues.","author":"Joseph R.","year":"2006"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.705525"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.338099"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2011.18"},{"key":"e_1_2_1_20_1","volume-title":"Proceedings of the 2011 IEEE 29th VLSI Test Symposium (VTS). 235--240","author":"Maniatakos M."},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.3"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.5555\/545215.545227"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.5555\/872021.872461"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555769"},{"key":"e_1_2_1_25_1","volume-title":"SESC: SuperESCalar Simulator","author":"J. Renau","year":"2005"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2011.5993813"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2011.82"},{"key":"e_1_2_1_28_1","volume-title":"Proceedings of the 2010 IEEE International Test Conference (ITC). 1--10","author":"Rodrigues R."},{"key":"e_1_2_1_29_1","volume-title":"Proceedings of the 2006 IEEE International Solid-State Circuits Conference (ISSCC\u201906)","author":"Rusu S.","year":"2006"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.44"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/PRDC.2013.44"},{"key":"e_1_2_1_32_1","unstructured":"P. Shivakumar N. P. Jouppi and P. Shivakumar. 2001. CACTI 3.0: An Integrated Cache Timing Power and Area Model. Technical Report.  P. Shivakumar N. P. Jouppi and P. Shivakumar. 2001. CACTI 3.0: An Integrated Cache Timing Power and Area Model. Technical Report."},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.5555\/946246.946573"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168868"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.28"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.237727"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.461.0005"},{"key":"e_1_2_1_38_1","volume-title":"Proceedings of the 2009 IEEE\/IFIP International Conference on Dependable Systems Networks (DSN\u201909)","author":"Weaver N.","year":"2009"}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2629688","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2629688","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T06:13:30Z","timestamp":1750227210000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2629688"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,1,21]]},"references-count":38,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2015,1,21]]}},"alternative-id":["10.1145\/2629688"],"URL":"https:\/\/doi.org\/10.1145\/2629688","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"value":"1539-9087","type":"print"},{"value":"1558-3465","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,1,21]]},"assertion":[{"value":"2012-12-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2014-03-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2015-01-21","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}