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However, aggressive voltage reduction causes process-variation-induced failures in cache SRAM arrays, thus compromising cache reliability. We present MultiCopy Cache (MC\n            <jats:sup>2<\/jats:sup>\n            ), a new cache architecture that achieves significant reduction in energy consumption through aggressive voltage scaling while maintaining high error resilience (reliability) by exploiting multiple copies of each data item in the cache. Unlike many previous approaches, MC\n            <jats:sup>2<\/jats:sup>\n            does not require any error map characterization and therefore is responsive to changing operating conditions (e.g., Vdd noise, temperature, and leakage) of the cache. MC\n            <jats:sup>2<\/jats:sup>\n            also incurs significantly lower overheads compared to other ECC-based caches. Our experimental results on embedded benchmarks demonstrate that MC\n            <jats:sup>2<\/jats:sup>\n            achieves up to 60% reduction in energy and energy-delay product (EDP) with only 3.5% reduction in IPC and no appreciable area overhead.\n          <\/jats:p>","DOI":"10.1145\/2632162","type":"journal-article","created":{"date-parts":[[2014,8,21]],"date-time":"2014-08-21T12:19:12Z","timestamp":1408623552000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Multicopy Cache"],"prefix":"10.1145","volume":"13","author":[{"given":"Arup","family":"Chakraborty","sequence":"first","affiliation":[{"name":"University of California, Irvine"}]},{"given":"Houman","family":"Homayoun","sequence":"additional","affiliation":[{"name":"University of California, San Diego"}]},{"given":"Amin","family":"Khajeh","sequence":"additional","affiliation":[{"name":"Qualcomm Inc., Austin, TX"}]},{"given":"Nikil","family":"Dutt","sequence":"additional","affiliation":[{"name":"University of California, Irvine"}]},{"given":"Ahmed","family":"Eltawil","sequence":"additional","affiliation":[{"name":"University of California, Irvine"}]},{"given":"Fadi","family":"Kurdahi","sequence":"additional","affiliation":[{"name":"University of California, Irvine"}]}],"member":"320","published-online":{"date-parts":[[2014,7,23]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1254766.1254773"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.840407"},{"key":"e_1_2_1_3_1","unstructured":"ARM. 2010. ARM cortex-a8 technical reference manual. http:\/\/www.arm.com\/products\/CPUs\/ARM_Cortex-A8.html.  ARM. 2010. ARM cortex-a8 technical reference manual. http:\/\/www.arm.com\/products\/CPUs\/ARM_Cortex-A8.html."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.982917"},{"key":"e_1_2_1_5_1","unstructured":"F. Behmann. 2009. Embedded.com - The itrs process roadmap and nextgen embedded multicore soc design. http:\/\/www.embedded.com\/design\/mcus-processors-and-socs\/4008253\/The-ITRS-process-roadmap-and-nextgen-embedded-multicore-SoC-design.  F. Behmann. 2009. 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Genua. 2004. A cache primer. http:\/\/www.csd.uwo.ca\/&sim;moreno\/CS433-CS9624\/Resources\/AN2663.pdf.  P. Genua. 2004. A cache primer. http:\/\/www.csd.uwo.ca\/&sim;moreno\/CS433-CS9624\/Resources\/AN2663.pdf."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.5555\/1128020.1128563"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.144.0395"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/383082.383086"},{"key":"e_1_2_1_20_1","unstructured":"ITRS. 2008. International technology roadmap for semiconductors. http:\/\/www.itrs.net\/Links\/2008ITRS\/home 2008.htm.  ITRS. 2008. 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