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Archit. Code Optim."],"published-print":{"date-parts":[[2014,10,27]]},"abstract":"<jats:p>\n            Many new nonvolatile memory (NVM) technologies have been heavily studied to replace the power-hungry SRAM\/DRAM-based memory hierarchy in today's computers. Among various emerging NVM technologies, Spin-Transfer Torque RAM (STT-RAM) has many benefits, such as fast read latency, low leakage power, and high density, making it a promising candidate for last-level caches (LLCs).\n            <jats:sup>1<\/jats:sup>\n            However, STT-RAM write operation is expensive. In particular, a long STT-RAM cache write operation might obstruct other cache accesses and result in severe performance degradation. Consequently, how to mitigate STT-RAM write overhead is critical to the success of STT-RAM adoption. In this article, we propose an obstruction-aware cache management policy called OAP. OAP monitors cache traffic, detects LLC-obstructive processes, and differentiates the cache accesses from different processes. Our experiment on a four-core architecture with an 8MB STT-RAM L3 cache shows a 14% performance improvement and 64% energy reduction.\n          <\/jats:p>","DOI":"10.1145\/2633046","type":"journal-article","created":{"date-parts":[[2014,8,1]],"date-time":"2014-08-01T20:13:24Z","timestamp":1406924004000},"page":"1-19","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["Preventing STT-RAM Last-Level Caches from Port Obstruction"],"prefix":"10.1145","volume":"11","author":[{"given":"Jue","family":"Wang","sequence":"first","affiliation":[{"name":"Pennsylvania State University"}]},{"given":"Xiangyu","family":"Dong","sequence":"additional","affiliation":[{"name":"Qualcomm Technology, Inc."}]},{"given":"Yuan","family":"Xie","sequence":"additional","affiliation":[{"name":"Pennsylvania State University"}]}],"member":"320","published-online":{"date-parts":[[2014,7,31]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391610"},{"key":"e_1_2_1_3_1","doi-asserted-by":"crossref","DOI":"10.1109\/TCAD.2012.2185930","article-title":"NVSim: A circuit-level performance, energy, and area model for emerging non-volatile memory","volume":"31","author":"Dong Xiangyu","year":"2012","unstructured":"Xiangyu Dong , Cong Xu , Yuan Xie , and Norm Jouppi . 2012 . NVSim: A circuit-level performance, energy, and area model for emerging non-volatile memory . IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31 , 0 (2012). Xiangyu Dong, Cong Xu, Yuan Xie, and Norm Jouppi. 2012. NVSim: A circuit-level performance, energy, and area model for emerging non-volatile memory. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, 0 (2012).","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"e_1_2_1_4_1","unstructured":"A. Driskill-Smith. 2011. Latest advances and future prospects of STT-RAM. In NVMW.  A. Driskill-Smith. 2011. Latest advances and future prospects of STT-RAM. In NVMW."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2013.16"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815971"},{"key":"e_1_2_1_7_1","doi-asserted-by":"crossref","unstructured":"T. Kawahara and others. 2007. 2Mb spin-transfer torque RAM (SPRAM) with bit-by-bit bidirectional current write and parallelizing-direction current read. In ISSCC.  T. Kawahara and others. 2007. 2Mb spin-transfer torque RAM (SPRAM) with bit-by-bit bidirectional current write and parallelizing-direction current read. In ISSCC.","DOI":"10.1109\/ISSCC.2007.373503"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/871506.871511"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/1025127.1026001"},{"key":"e_1_2_1_10_1","volume-title":"Proceedings of the International Symposium on Computer Architecture. 81--87","author":"Kroft David","year":"1981","unstructured":"David Kroft . 1981 . Lockup-free instruction fetch\/prefetch cache organization . In Proceedings of the International Symposium on Computer Architecture. 81--87 . David Kroft. 1981. Lockup-free instruction fetch\/prefetch cache organization. In Proceedings of the International Symposium on Computer Architecture. 81--87."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.501.0025"},{"key":"e_1_2_1_12_1","doi-asserted-by":"crossref","unstructured":"Kumiko Nomura Keiko Abe Hiroaki Yoda and Shinobu Fujita. 2011. Ultra low power processor using perpendicular-STTMRAM\/SRAM based hybrid cache toward next generation normally-off computers. In MMM.  Kumiko Nomura Keiko Abe Hiroaki Yoda and Shinobu Fujita. 2011. Ultra low power processor using perpendicular-STTMRAM\/SRAM based hybrid cache toward next generation normally-off computers. In MMM.","DOI":"10.1063\/1.3677444"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.49"},{"key":"e_1_2_1_14_1","unstructured":"Hari M. Rao and Jung Pill Kim. Multi-port non-volatile memory that includes a resistive memory element. U.S. Patent Application 13\/772 411.  Hari M. Rao and Jung Pill Kim. Multi-port non-volatile memory that includes a resistive memory element. U.S. Patent Application 13\/772 411."},{"volume-title":"2011 IEEE 17th International Symposium on High Performance Computer Architecture (HPCA). 50--61","author":"Smullen Clinton W.","key":"e_1_2_1_15_1","unstructured":"Clinton W. Smullen , Mohan Vidyabhushan , Anurag Nigam , Sudhanva Gurumurthi , and Mircea R. Stan . Relaxing non-volatility for fast and energy-efficient STT-RAM caches . In 2011 IEEE 17th International Symposium on High Performance Computer Architecture (HPCA). 50--61 . Clinton W. Smullen, Mohan Vidyabhushan, Anurag Nigam, Sudhanva Gurumurthi, and Mircea R. Stan. Relaxing non-volatility for fast and energy-efficient STT-RAM caches. In 2011 IEEE 17th International Symposium on High Performance Computer Architecture (HPCA). 50--61."},{"key":"e_1_2_1_16_1","volume-title":"SPEC CPU2006","author":"SPEC","year":"2006","unstructured":"SPEC CPU. 2006 . SPEC CPU2006 . Retrieved from http:\/\/www.spec.org\/cpu 2006\/. SPEC CPU. 2006. SPEC CPU2006. Retrieved from http:\/\/www.spec.org\/cpu2006\/."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669177"},{"key":"e_1_2_1_18_1","doi-asserted-by":"crossref","unstructured":"Sun Guangyu Xiangyu Dong Yuan Xie Jian Li and Yiran Chen. 2009. A novel architecture of the 3D stacked MRAM L2 cache for CMPs. In High Performance Computer Architecture. 239--249.  Sun Guangyu Xiangyu Dong Yuan Xie Jian Li and Yiran Chen. 2009. A novel architecture of the 3D stacked MRAM L2 cache for CMPs. In High Performance Computer Architecture. 239--249.","DOI":"10.1109\/HPCA.2009.4798259"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155659"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.16"},{"key":"e_1_2_1_21_1","volume-title":"International Solid-State Circuits Conference Digest of Technical Papers (ISSCC). 258--259","author":"Tsuchida Kenji","year":"2010","unstructured":"Kenji Tsuchida , Tsuneo Inaba , Katsuyuki Fujita , Yoshihiro Ueda , Takafumi Shimizu , Yoshiaki Asao , Takeshi Kajiyama , Masayoshi Iwayama , Kuniaki Sugiura , Sumio Ikegawa , Tatsuya Kishi , Tadashi Kai , Minoru Amano , Naoharu Shimomura , Hiroaki Yoda , and Yohji Watanabe . 2010 . A 64Mb MRAM with clamped-reference and adequate-reference schemes. 2010 . In International Solid-State Circuits Conference Digest of Technical Papers (ISSCC). 258--259 . Kenji Tsuchida, Tsuneo Inaba, Katsuyuki Fujita, Yoshihiro Ueda, Takafumi Shimizu, Yoshiaki Asao, Takeshi Kajiyama, Masayoshi Iwayama, Kuniaki Sugiura, Sumio Ikegawa, Tatsuya Kishi, Tadashi Kai, Minoru Amano, Naoharu Shimomura, Hiroaki Yoda, and Yohji Watanabe. 2010. A 64Mb MRAM with clamped-reference and adequate-reference schemes. 2010. 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