{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,5]],"date-time":"2026-10-05T09:03:08Z","timestamp":1791190988774,"version":"4.1.0"},"publisher-location":"New York, NY, USA","reference-count":7,"publisher":"ACM","license":[{"start":{"date-parts":[[2014,6,1]],"date-time":"2014-06-01T00:00:00Z","timestamp":1401580800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2014,6]]},"DOI":"10.1145\/2633948.2633951","type":"proceedings-article","created":{"date-parts":[[2014,8,13]],"date-time":"2014-08-13T20:33:47Z","timestamp":1407962027000},"page":"1-5","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["PACMAN"],"prefix":"10.1145","author":[{"given":"Nancy Y.","family":"Zhou","sequence":"first","affiliation":[{"name":"IBM Systems & Technology Group, 11400 Burnet Road, Austin, TX 78758"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Phillip","family":"Restle","sequence":"additional","affiliation":[{"name":"IBM Waston Research Laboratory, 11501 Burnet Road, Austin, TX 78758"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Joseph","family":"Palumbo","sequence":"additional","affiliation":[{"name":"IBM Waston Research Laboratory, 11501 Burnet Road, Austin, TX 78758"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Joseph","family":"Kozhaya","sequence":"additional","affiliation":[{"name":"IBM Systems & Technology Group, 11400 Burnet Road, Austin, TX 78758"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Haifeng","family":"Qian","sequence":"additional","affiliation":[{"name":"IBM Waston Research Laboratory, 11501 Burnet Road, Austin, TX 78758"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zhuo","family":"Li","sequence":"additional","affiliation":[{"name":"IBM Waston Research Laboratory, 11501 Burnet Road, Austin, TX 78758"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Charles J.","family":"Alpert","sequence":"additional","affiliation":[{"name":"IBM Waston Research Laboratory, 11501 Burnet Road, Austin, TX 78758"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Cliff","family":"Sze","sequence":"additional","affiliation":[{"name":"IBM Waston Research Laboratory, 11501 Burnet Road, Austin, TX 78758"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2014,6]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"346","volume-title":"Solid-State Circuits Conference.","author":"Bindal N.","year":"2003","unstructured":"N. Bindal , T. Kelly , N. Velastegui and K. L. Wong , \" Scalable sub-10 ps skew global clock distribution for a 90nm multi-GHZ 1A microprocessor,\" in Proceedings of IEEE Int . Solid-State Circuits Conference. pp. 346 -- 347 , 2003 . N. Bindal, T. Kelly, N. Velastegui and K. L. Wong, \"Scalable sub-10 ps skew global clock distribution for a 90nm multi-GHZ 1A microprocessor,\" in Proceedings of IEEE Int. Solid-State Circuits Conference. pp. 346--347, 2003."},{"key":"e_1_3_2_1_2_1","volume-title":"X-Y grid tree clock distribution network with tunable tree and grid networks,\" in U.S. Patent 6311313","author":"Camporese P. J.","year":"2001","unstructured":"P. J. Camporese , A. Deutsch , T. G. McNamara , P. J. Restle and D. A. Webber , \" X-Y grid tree clock distribution network with tunable tree and grid networks,\" in U.S. Patent 6311313 . 2001 . P. J. Camporese, A. Deutsch, T. G. McNamara, P. J. Restle and D. A. Webber, \"X-Y grid tree clock distribution network with tunable tree and grid networks,\" in U.S. Patent 6311313. 2001."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/127601.127688"},{"key":"e_1_3_2_1_4_1","first-page":"292","volume-title":"Solid-State Circuits Conference.","author":"Mahoney P.","year":"2005","unstructured":"P. Mahoney , E. Fetzer , B. Doyle and S. Naffziger , \" Clock distribution on a dual-core multi-threaded Itanium-family processor,\" in Proceedings of IEEE Int . Solid-State Circuits Conference. pp. 292 -- 293 , 2005 . P. Mahoney, E. Fetzer, B. Doyle and S. Naffziger, \"Clock distribution on a dual-core multi-threaded Itanium-family processor,\" in Proceedings of IEEE Int. Solid-State Circuits Conference. pp. 292--293, 2005."},{"key":"e_1_3_2_1_5_1","first-page":"271","article-title":"Myth Busters: Microprocessor Clocking is from Mars, ASIC Clocking is from Venus","author":"Kozhaya J. N.","year":"2011","unstructured":"J. N. Kozhaya , P. J. Restle and H. Qian \" Myth Busters: Microprocessor Clocking is from Mars, ASIC Clocking is from Venus ,\" in ICCAD 2011 , pp. 271 -- 275 , 2011. J. N. Kozhaya, P. J. Restle and H. Qian \"Myth Busters: Microprocessor Clocking is from Mars, ASIC Clocking is from Venus,\" in ICCAD 2011, pp. 271--275, 2011.","journal-title":"ICCAD"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.918917"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2182767"}],"event":{"name":"SLIP '14: System Level Interconnect Prediction Workshop","location":"San Francisco CA USA","acronym":"SLIP '14","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CS"]},"container-title":["Proceedings of SLIP (System Level Interconnect Prediction) on System Level Interconnect Prediction Workshop"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2633948.2633951","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2633948.2633951","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T06:55:56Z","timestamp":1750229756000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2633948.2633951"}},"subtitle":["Driving Nonuniform Clock Grid Loads for low-skew robust clock network"],"short-title":[],"issued":{"date-parts":[[2014,6]]},"references-count":7,"alternative-id":["10.1145\/2633948.2633951","10.1145\/2633948"],"URL":"https:\/\/doi.org\/10.1145\/2633948.2633951","relation":{},"subject":[],"published":{"date-parts":[[2014,6]]},"assertion":[{"value":"2014-06-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}