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The first approach is the classical CORDIC iteration, for which we suggest a reduced iteration technique and fine optimizations in datapath width and latency. The second is an ad-hoc architecture specifically designed around trigonometric identities. The third uses a generic table- and DSP-based polynomial approximator. These three architectures are implemented and compared in the FloPoCo framework.<\/jats:p>","DOI":"10.1145\/2641361.2641375","type":"journal-article","created":{"date-parts":[[2014,7,7]],"date-time":"2014-07-07T11:55:18Z","timestamp":1404734118000},"page":"83-88","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":22,"title":["Fixed-point trigonometric functions on FPGAs"],"prefix":"10.1145","volume":"41","author":[{"given":"Florent","family":"de Dinechin","sequence":"first","affiliation":[{"name":"Universit\u00e9 de Lyon, Lyon Cedex, France"}]},{"given":"Matei","family":"Istoan","sequence":"additional","affiliation":[{"name":"Universit\u00e9 de Lyon, Lyon Cedex, France"}]},{"given":"Guillaume","family":"Sergent","sequence":"additional","affiliation":[{"name":"Universit\u00e9 de Lyon, Lyon Cedex, France"}]}],"member":"320","published-online":{"date-parts":[[2014,6,18]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275139"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-28365-9_5"},{"key":"e_1_2_1_3_1","volume-title":"Oct.","author":"De Dinechin F.","year":"2012","unstructured":"F. De Dinechin , M. Istoan , G. Sergent , K. Illyes , B. Popa , and N. Brunie . Arithmetic around the bit heap. Technical report , Oct. 2012 . F. De Dinechin, M. Istoan, G. Sergent, K. Illyes, B. Popa, and N. Brunie. Arithmetic around the bit heap. Technical report, Oct. 2012."},{"key":"e_1_2_1_4_1","volume-title":"Application-specific Systems, Architectures and Processors","author":"de Dinechin F.","year":"2010","unstructured":"F. de Dinechin , M. Joldes , and B. Pasca . Automatic generation of polynomial-based hardware architectures for function evaluation . In Application-specific Systems, Architectures and Processors . IEEE , 2010 . F. de Dinechin, M. Joldes, and B. Pasca. Automatic generation of polynomial-based hardware architectures for function evaluation. In Application-specific Systems, Architectures and Processors. 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CORDIC v4.0 (DSD249), 2009."}],"container-title":["ACM SIGARCH Computer Architecture News"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2641361.2641375","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2641361.2641375","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T20:01:07Z","timestamp":1750276867000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2641361.2641375"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,12,18]]},"references-count":12,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2013,12,18]]}},"alternative-id":["10.1145\/2641361.2641375"],"URL":"https:\/\/doi.org\/10.1145\/2641361.2641375","relation":{},"ISSN":["0163-5964"],"issn-type":[{"value":"0163-5964","type":"print"}],"subject":[],"published":{"date-parts":[[2013,12,18]]},"assertion":[{"value":"2014-06-18","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}