{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T12:08:21Z","timestamp":1759147701990,"version":"3.41.0"},"reference-count":46,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2014,8,1]],"date-time":"2014-08-01T00:00:00Z","timestamp":1406851200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100001659","name":"Deutsche Forschungsgemeinschaft","doi-asserted-by":"publisher","award":["WU245\/11-1 (OASIS)"],"award-info":[{"award-number":["WU245\/11-1 (OASIS)"]}],"id":[{"id":"10.13039\/501100001659","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2014,8]]},"abstract":"<jats:p>As the technology shrinks, nonfunctional properties (NFPs) such as reliability, vulnerability, power consumption, or heat dissipation become as important as system functionality. As NFPs often influence each other, depend on the application and workload of a system, and exhibit nonlinear behavior, NFP simulation over long periods of system operation is computationally expensive, if feasible at all.<\/jats:p>\n          <jats:p>\n            This article presents a piecewise evaluation method for efficient NFP simulation. Simulation time is divided into intervals called\n            <jats:italic>evaluation windows<\/jats:italic>\n            , within which the NFP models are partially linearized. High-speed functional system simulation is achieved by parallel execution of models at different levels of abstraction. A trade-off between simulation speed and accuracy is met by adjusting the size of the evaluation window.\n          <\/jats:p>\n          <jats:p>As an example, the piecewise evaluation technique is applied to analyze aging caused by two mechanisms, namely Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI), in order to identify reliability hotspots. Experiments show that the proposed technique yields considerable simulation speedup at a marginal loss of accuracy.<\/jats:p>","DOI":"10.1145\/2647955","type":"journal-article","created":{"date-parts":[[2014,8,26]],"date-time":"2014-08-26T12:08:55Z","timestamp":1409054935000},"page":"1-21","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Multilevel Simulation of Nonfunctional Properties by Piecewise Evaluation"],"prefix":"10.1145","volume":"19","author":[{"given":"Nadereh","family":"Hatami","sequence":"first","affiliation":[{"name":"University of Stuttgart, Stuttgart, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rafal","family":"Baranowski","sequence":"additional","affiliation":[{"name":"University of Stuttgart, Stuttgart, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Paolo","family":"Prinetto","sequence":"additional","affiliation":[{"name":"Politecnico di Torino, Torino TO, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hans-Joachim","family":"Wunderlich","sequence":"additional","affiliation":[{"name":"University of Stuttgart, Stuttgart, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2014,8,29]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2004.03.019"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/214282.214336"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11432-011-4366-9"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2005.12.004"},{"volume-title":"Proceedings of the Custom Integrated Circuits Conference (CICC'06)","author":"Bhardwaj S.","key":"e_1_2_1_5_1","unstructured":"S. Bhardwaj , W. Wang , R. Vattikonda , Y. Cao , and S. Vrudhula . 2006. Predictive modeling of the nbti effect for reliable design . In Proceedings of the Custom Integrated Circuits Conference (CICC'06) . 189--192. S. Bhardwaj, W. Wang, R. Vattikonda, Y. Cao, and S. Vrudhula. 2006. Predictive modeling of the nbti effect for reliable design. In Proceedings of the Custom Integrated Circuits Conference (CICC'06). 189--192."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/342001.339657"},{"volume-title":"Predictive Technology Model for Robust Nanoelectronic Design","author":"Cao Y.","key":"e_1_2_1_7_1","unstructured":"Y. Cao . 2011. Predictive Technology Model for Robust Nanoelectronic Design . Springer . Y. Cao. 2011. Predictive Technology Model for Robust Nanoelectronic Design. Springer."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/217474.217520"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630056"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2206781.2206793"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10766-009-0104-y"},{"volume-title":"Proceedings of the East-West Design and Test Symposium (EWDTS'08)","author":"English T.","key":"e_1_2_1_12_1","unstructured":"T. English , K. L. Man , E. Popovici , and M. P. Schellekens . 2008. HotSpot: Visualizing dynamic power consumption in RTL designs . In Proceedings of the East-West Design and Test Symposium (EWDTS'08) . 45--48. T. English, K. L. Man, E. Popovici, and M. P. Schellekens. 2008. HotSpot: Visualizing dynamic power consumption in RTL designs. In Proceedings of the East-West Design and Test Symposium (EWDTS'08). 45--48."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/84537.84545"},{"volume-title":"2005. Transaction-Level Modeling with Systemc - TLM Concepts and Applications for Embedded Systems","author":"Ghenassia F.","key":"e_1_2_1_14_1","unstructured":"F. Ghenassia . Ed. 2005. Transaction-Level Modeling with Systemc - TLM Concepts and Applications for Embedded Systems . Springer . F. Ghenassia. Ed. 2005. Transaction-Level Modeling with Systemc - TLM Concepts and Applications for Embedded Systems. Springer."},{"volume-title":"Proceedings of the ACM\/IEEE Design Automation Conference (DAC'92)","author":"Ghosh A.","key":"e_1_2_1_15_1","unstructured":"A. Ghosh , S. Devadas , K. Keutzer , and J. White . 1992. Estimation of average switching activity in combinational and sequential circuits . In Proceedings of the ACM\/IEEE Design Automation Conference (DAC'92) . 253--259. A. Ghosh, S. Devadas, K. Keutzer, and J. White. 1992. Estimation of average switching activity in combinational and sequential circuits. In Proceedings of the ACM\/IEEE Design Automation Conference (DAC'92). 253--259."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/RE.2007.45"},{"volume-title":"Proceedings of the European Test Symposium (ETS'12)","author":"Hatami N.","key":"e_1_2_1_17_1","unstructured":"N. Hatami , R. Baranowski , P. Prinetto , and H. Wunderlich . 2012. Efficient system-level aging prediction . In Proceedings of the European Test Symposium (ETS'12) . 1--6. N. Hatami, R. Baranowski, P. Prinetto, and H. Wunderlich. 2012. Efficient system-level aging prediction. In Proceedings of the European Test Symposium (ETS'12). 1--6."},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.876103"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996800"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2017751"},{"volume-title":"Proceedings of the Design, Automation, and Test in Europe Conference (DATE'11)","author":"Kim D.","key":"e_1_2_1_21_1","unstructured":"D. Kim , M. Ciesielski , and S. Yang . 2011a. A new distributed event-driven gate-level HDL simulation by accurate prediction . In Proceedings of the Design, Automation, and Test in Europe Conference (DATE'11) . 1--4. D. Kim, M. Ciesielski, and S. Yang. 2011a. A new distributed event-driven gate-level HDL simulation by accurate prediction. In Proceedings of the Design, Automation, and Test in Europe Conference (DATE'11). 1--4."},{"volume-title":"Proceedings of the Design, Automation, and Test in Europe Conference (DATE'11)","author":"Kim D.","key":"e_1_2_1_22_1","unstructured":"D. Kim , M. Ciesielski , K. Shim , and S. Yang . 2011b. Temporal parallel simulation: A fast gate-level HDL simulation using higher level models . In Proceedings of the Design, Automation, and Test in Europe Conference (DATE'11) . 1584--1589. D. Kim, M. Ciesielski, K. Shim, and S. Yang. 2011b. Temporal parallel simulation: A fast gate-level HDL simulation using higher level models. In Proceedings of the Design, Automation, and Test in Europe Conference (DATE'11). 1584--1589."},{"volume-title":"Proceedings of the Canadian Conference on Electrical and Computer Engineering. 438--445","author":"Kwong A. L.-C.","key":"e_1_2_1_23_1","unstructured":"A. L.-C. Kwong , B. F. Cockburn , and D. G. Elliott . 1999. Dynamic combined pattern-parallel and fault-parallel fault simulation on computational RAM . In Proceedings of the Canadian Conference on Electrical and Computer Engineering. 438--445 . A. L.-C. Kwong, B. F. Cockburn, and D. G. Elliott. 1999. Dynamic combined pattern-parallel and fault-parallel fault simulation on computational RAM. In Proceedings of the Canadian Conference on Electrical and Computer Engineering. 438--445."},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.mee.2007.04.022"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/16.52430"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2011.12.029"},{"volume-title":"Proceedings of the International On-Line Testing Symposium (IOLTS'09)","author":"Lorenz D.","key":"e_1_2_1_28_1","unstructured":"D. Lorenz , G. Georgakos , and U. Schlichtmann . 2009. Aging analysis of circuit timing considering NBTI and hci . In Proceedings of the International On-Line Testing Symposium (IOLTS'09) . 3--8. D. Lorenz, G. Georgakos, and U. Schlichtmann. 2009. Aging analysis of circuit timing considering NBTI and hci. In Proceedings of the International On-Line Testing Symposium (IOLTS'09). 3--8."},{"volume-title":"Proceedings of the International SoC Design Conference (ISOCC'11)","author":"Man K. L.","key":"e_1_2_1_29_1","unstructured":"K. L. Man , J. Ma , T. T. Jeong , C.-U. Lei , Y. Wu , S.-U. Guan , J. K. Seon , and Y. Lee . 2011. Design, analysis, tools and applications for programmable high-speed and power-aware 4g processors . In Proceedings of the International SoC Design Conference (ISOCC'11) . 321--324. K. L. Man, J. Ma, T. T. Jeong, C.-U. Lei, Y. Wu, S.-U. Guan, J. K. Seon, and Y. Lee. 2011. Design, analysis, tools and applications for programmable high-speed and power-aware 4g processors. In Proceedings of the International SoC Design Conference (ISOCC'11). 321--324."},{"volume-title":"Proceedings of the International Symposium on Microarchitecture (MICRO'03)","author":"Mukherjee S. S.","key":"e_1_2_1_30_1","unstructured":"S. S. Mukherjee , C. Weaver , J. Emer , S. K. Reinhardt , and T. Austin . 2003. A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor . In Proceedings of the International Symposium on Microarchitecture (MICRO'03) . 29--40. S. S. Mukherjee, C. Weaver, J. Emer, S. K. Reinhardt, and T. Austin. 2003. A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor. In Proceedings of the International Symposium on Microarchitecture (MICRO'03). 29--40."},{"volume-title":"Proceedings of the European Test Symposium (ETS'10)","author":"Noda M.","key":"e_1_2_1_31_1","unstructured":"M. Noda , S. Kajihara , Y. Sato , K. Miyase , X. Wen , and Y. Miura . 2010. On estimation of NBTI-induced delay degradation . In Proceedings of the European Test Symposium (ETS'10) . 107--111. M. Noda, S. Kajihara, Y. Sato, K. Miyase, X. Wen, and Y. Miura. 2010. On estimation of NBTI-induced delay degradation. In Proceedings of the European Test Symposium (ETS'10). 107--111."},{"volume-title":"Proceedings of the International Conference on Dependable Systems and Networks (DSN'12)","author":"Oboril F.","key":"e_1_2_1_32_1","unstructured":"F. Oboril and M. B. Tahoori . 2012. Extratime: Modeling and analysis of wearout due to transistor aging at microarchitecture-level . In Proceedings of the International Conference on Dependable Systems and Networks (DSN'12) . 1--12. F. Oboril and M. B. Tahoori. 2012. Extratime: Modeling and analysis of wearout due to transistor aging at microarchitecture-level. In Proceedings of the International Conference on Dependable Systems and Networks (DSN'12). 1--12."},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2002.1047740"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.879797"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403566"},{"key":"e_1_2_1_36_1","doi-asserted-by":"crossref","unstructured":"J. Segura and F. C. Hawkins. 2004. CMOS Electronics: How It Works How It Fails. Wiley\/IEEE Press.   J. Segura and F. C. Hawkins. 2004. CMOS Electronics: How It Works How It Fails. Wiley\/IEEE Press.","DOI":"10.1002\/0471728527"},{"volume-title":"Proceedings of the IEEE Workshop on Signal Processing Systems (SiPS'99)","author":"Shim K.","key":"e_1_2_1_37_1","unstructured":"K. Shim , I. K. Oh , S. M. Hong , B. S. Ryu , K. Y. Lee , and T. W. Cho . 1999. A multi-level approach to low power MAC design . In Proceedings of the IEEE Workshop on Signal Processing Systems (SiPS'99) . 723-- 731. K. Shim, I. K. Oh, S. M. Hong, B. S. Ryu, K. Y. Lee, and T. W. Cho. 1999. A multi-level approach to low power MAC design. In Proceedings of the IEEE Workshop on Signal Processing Systems (SiPS'99). 723-- 731."},{"volume-title":"Proceedings of the International Conference on Dependable Systems and Networks (DSN'04)","author":"Srinivasan J.","key":"e_1_2_1_38_1","unstructured":"J. Srinivasan , S. V. Adve , P. Bose , and J. A. Rivers . 2004. The impact of technology scaling on lifetime reliability . In Proceedings of the International Conference on Dependable Systems and Networks (DSN'04) . 177--186. J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers. 2004. The impact of technology scaling on lifetime reliability. In Proceedings of the International Conference on Dependable Systems and Networks (DSN'04). 177--186."},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/MTV.2007.8"},{"key":"e_1_2_1_40_1","doi-asserted-by":"crossref","unstructured":"A. Viehl B. Sander O. Bringmann and W. Rosenstiel. 2009. Analysis of non-functional properties of MPSoC designs. In Languages for Embedded Systems and their Applications M. Radetzki Ed. Springer 309--324.  A. Viehl B. Sander O. Bringmann and W. Rosenstiel. 2009. Analysis of non-functional properties of MPSoC designs. In Languages for Embedded Systems and their Applications M. Radetzki Ed. Springer 309--324.","DOI":"10.1007\/978-1-4020-9714-0_20"},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2009.29"},{"volume-title":"Proceedings of the Design, Automation, and Test in Europe Conference (DATE'07)","author":"Wang Y.","key":"e_1_2_1_42_1","unstructured":"Y. Wang , H. Luo , K. He , R. Luo , H. Yang , and Y. Xie . 2007a. Temperature-aware nbti modeling and the impact of input vector control on performance degradation . In Proceedings of the Design, Automation, and Test in Europe Conference (DATE'07) . 546--551. Y. Wang, H. Luo, K. He, R. Luo, H. Yang, and Y. Xie. 2007a. Temperature-aware nbti modeling and the impact of input vector control on performance degradation. In Proceedings of the Design, Automation, and Test in Europe Conference (DATE'07). 546--551."},{"key":"e_1_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2007.910130"},{"volume-title":"Proceedings of the International Conference on Computer-Aided Design (ICCAD'07)","author":"Wang W.","key":"e_1_2_1_44_1","unstructured":"W. Wang , Z. Wei , S. Yang , and Y. Cao . 2007c. An efficient method to identify critical gates under circuit aging . In Proceedings of the International Conference on Computer-Aided Design (ICCAD'07) . 735--740. W. Wang, Z. Wei, S. Yang, and Y. Cao. 2007c. An efficient method to identify critical gates under circuit aging. In Proceedings of the International Conference on Computer-Aided Design (ICCAD'07). 735--740."},{"key":"e_1_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278573"},{"key":"e_1_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2008810"}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2647955","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2647955","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T07:19:40Z","timestamp":1750231180000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2647955"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,8]]},"references-count":46,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2014,8]]}},"alternative-id":["10.1145\/2647955"],"URL":"https:\/\/doi.org\/10.1145\/2647955","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"type":"print","value":"1084-4309"},{"type":"electronic","value":"1557-7309"}],"subject":[],"published":{"date-parts":[[2014,8]]},"assertion":[{"value":"2013-10-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2014-04-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2014-08-29","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}