{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:18:53Z","timestamp":1750306733274,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":30,"publisher":"ACM","license":[{"start":{"date-parts":[[2014,10,8]],"date-time":"2014-10-08T00:00:00Z","timestamp":1412726400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2014,10,8]]},"DOI":"10.1145\/2659787.2659816","type":"proceedings-article","created":{"date-parts":[[2014,10,1]],"date-time":"2014-10-01T13:35:08Z","timestamp":1412170508000},"page":"77-86","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["The Boot Process in Real-time Manycore Processors"],"prefix":"10.1145","author":[{"given":"Florian","family":"Kluge","sequence":"first","affiliation":[{"name":"Department of Computer Science, University of Augsburg, 86159 Augsburg, Germany"}]},{"given":"Mike","family":"Gerdes","sequence":"additional","affiliation":[{"name":"Department of Computer Science, University of Augsburg, 86159 Augsburg, Germany"}]},{"given":"Theo","family":"Ungerer","sequence":"additional","affiliation":[{"name":"Department of Computer Science, University of Augsburg, 86159 Augsburg, Germany"}]}],"member":"320","published-online":{"date-parts":[[2014,10,8]]},"reference":[{"doi-asserted-by":"publisher","key":"e_1_3_2_1_1_1","DOI":"10.1109\/ISORC.2013.6913225"},{"unstructured":"Adapteva Inc. Lexington MA USA. E16G301 EPIPHANY#8482;16-CORE MICROPROCESSOR Datasheet 14.2.21 edition 2013.  Adapteva Inc. Lexington MA USA. E16G301 EPIPHANY#8482;16-CORE MICROPROCESSOR Datasheet 14.2.21 edition 2013.","key":"e_1_3_2_1_2_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_3_1","DOI":"10.5555\/1927882.1927891"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_4_1","DOI":"10.1109\/DATE.2005.36"},{"key":"e_1_3_2_1_5_1","first-page":"29","volume-title":"Signals and Communication Technology","author":"Crippa L.","year":"2008"},{"volume-title":"4th symposium of the Many-core Applications Research Community (MARC)","year":"2011","author":"D'Ausbourg B.","key":"e_1_3_2_1_6_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_7_1","DOI":"10.1109\/HPEC.2013.6670342"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_8_1","DOI":"10.1109\/MDT.2005.99"},{"unstructured":"A.\n       \n      Gustavsson A.\n       \n      Ermedahl B.\n       \n      Lisper and \n      \n      \n      P.\n       \n      Pettersson\n      \n  \n  . \n  Towards WCET Analysis of Multicore Architectures Using UPPAAL. In B. Lisper editor 10th International Workshop on Worst-Case Execution Time Analysis (WCET\n   \n  2010\n  ) volume \n  15\n   of \n  OpenAccess Series in Informatics (OASIcs) pages \n  101\n  --\n  112 Dagstuhl Germany 2010. Schloss Dagstuhl--Leibniz-Zentrum fuer \n  Informatik\n  .  A. Gustavsson A. Ermedahl B. Lisper and P. Pettersson. Towards WCET Analysis of Multicore Architectures Using UPPAAL. In B. Lisper editor 10th International Workshop on Worst-Case Execution Time Analysis (WCET 2010) volume 15 of OpenAccess Series in Informatics (OASIcs) pages 101--112 Dagstuhl Germany 2010. Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik.","key":"e_1_3_2_1_9_1"},{"unstructured":"A.\n       \n      Gustavsson J.\n       \n      Gustafsson and \n      \n      \n      B.\n       \n      Lisper\n      \n  \n  . \n  Toward Static Timing Analysis of Parallel Software. In T. Vardanega editor 12th International Workshop on Worst-Case Execution Time Analysis volume \n  23\n   of \n  OpenAccess Series in Informatics (OASIcs) pages \n  38\n  --\n  47 Dagstuhl Germany 2012\n  . Schloss Dagstuhl--Leibniz-Zentrum fuer \n  Informatik\n  .  A. Gustavsson J. Gustafsson and B. Lisper. Toward Static Timing Analysis of Parallel Software. In T. Vardanega editor 12th International Workshop on Worst-Case Execution Time Analysis volume 23 of OpenAccess Series in Informatics (OASIcs) pages 38--47 Dagstuhl Germany 2012. Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik.","key":"e_1_3_2_1_10_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_11_1","DOI":"10.1109\/ISSCC.2010.5434077"},{"volume-title":"Corporation. News Fact Sheet: Intel Many Integrated Core (Intel MIC) Architecture ISC'11 Demos and Performance Description","year":"2011","key":"e_1_3_2_1_12_1"},{"unstructured":"Intel Corporation. Intel\u00ae Xeon Phi#8482; Coprocessor System Software Developers Guide sku#328207-002en edition June 2013.  Intel Corporation. Intel\u00ae Xeon Phi#8482; Coprocessor System Software Developers Guide sku#328207-002en edition June 2013.","key":"e_1_3_2_1_13_1"},{"unstructured":"L. Julliard. The Kalray manycore solution May 2014. Talk at meeting of BICCnet AK Multicore Munich Germany.  L. Julliard. The Kalray manycore solution May 2014. Talk at meeting of BICCnet AK Multicore Munich Germany.","key":"e_1_3_2_1_14_1"},{"unstructured":"KALRAY Corporation. Kalray MPPA 256 processor 2013. retrieved Dec. 2013.  KALRAY Corporation. Kalray MPPA 256 processor 2013. retrieved Dec. 2013.","key":"e_1_3_2_1_15_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_16_1","DOI":"10.1109\/ISORC.2014.30"},{"volume-title":"Proceedings of 8th annual workshop on Operating Systems for Embedded Real-Time applications (OSPERT 2012","year":"2012","author":"Kluge F.","key":"e_1_3_2_1_17_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_18_1","DOI":"10.5555\/876891.880569"},{"volume-title":"Work-in-Progress Session of the 32nd IEEE Real-Time Systems Symposium (RTSS 2011","year":"2011","author":"Metzlaff S.","key":"e_1_3_2_1_19_1"},{"doi-asserted-by":"crossref","unstructured":"S. Metzlaff and T. Ungerer. A comparison of instruction memories from the WCET perspective. Journal of Systems Architecture - Embedded Systems Design 60(5):452--466 2014.  S. Metzlaff and T. Ungerer. A comparison of instruction memories from the WCET perspective. Journal of Systems Architecture - Embedded Systems Design 60(5):452--466 2014.","key":"e_1_3_2_1_20_1","DOI":"10.1016\/j.sysarc.2013.09.009"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_21_1","DOI":"10.1145\/2609248.2609261"},{"volume-title":"Freescale Semiconductor","year":"2008","author":"Peters T.","key":"e_1_3_2_1_22_1"},{"unstructured":"D.\n       \n      Potop-Butucaru\n     and \n      \n      \n      I.\n       \n      Puaut\n      \n  \n  . \n  Integrated Worst-Case Execution Time Estimation of Multicore Applications. In C. Maiza editor 13th International Workshop on Worst-Case Execution Time Analysis volume \n  30\n   of \n  OpenAccess Series in Informatics (OASIcs) pages \n  21\n  --\n  31 Dagstuhl Germany 2013\n  . Schloss Dagstuhl--Leibniz-Zentrum fuer \n  Informatik\n  .  D. Potop-Butucaru and I. Puaut. Integrated Worst-Case Execution Time Estimation of Multicore Applications. In C. Maiza editor 13th International Workshop on Worst-Case Execution Time Analysis volume 30 of OpenAccess Series in Informatics (OASIcs) pages 21--31 Dagstuhl Germany 2013. Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik.","key":"e_1_3_2_1_23_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_24_1","DOI":"10.1109\/NOCS.2012.25"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_25_1","DOI":"10.1109\/TC.2012.117"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_26_1","DOI":"10.5555\/850928.851853"},{"unstructured":"D 8.2 T-CREST White Paper Oct. 2013.  D 8.2 T-CREST White Paper Oct. 2013.","key":"e_1_3_2_1_27_1"},{"unstructured":"Tilera Corporation. TILE-Gx8036 Processor Specification Brief. Tilera Corporation 2011.  Tilera Corporation. TILE-Gx8036 Processor Specification Brief. Tilera Corporation 2011.","key":"e_1_3_2_1_28_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_29_1","DOI":"10.1109\/DSD.2013.46"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_30_1","DOI":"10.1109\/ISSCC.2007.373606"}],"event":{"sponsor":["CEA Commissariat \u00e0 l'\u00e9nergie atomique et aux \u00e9nergies alternatives","GDR ASR GDR Architecture, Syst\u00e8mes et R\u00e9seaux"],"acronym":"RTNS '14","name":"RTNS '14: 22nd International Conference on Real-Time Networks and Systems","location":"Versaille France"},"container-title":["Proceedings of the 22nd International Conference on Real-Time Networks and Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2659787.2659816","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2659787.2659816","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T07:19:47Z","timestamp":1750231187000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2659787.2659816"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,10,8]]},"references-count":30,"alternative-id":["10.1145\/2659787.2659816","10.1145\/2659787"],"URL":"https:\/\/doi.org\/10.1145\/2659787.2659816","relation":{},"subject":[],"published":{"date-parts":[[2014,10,8]]},"assertion":[{"value":"2014-10-08","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}