{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T10:03:49Z","timestamp":1767261829652,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":29,"publisher":"ACM","license":[{"start":{"date-parts":[[2014,10,8]],"date-time":"2014-10-08T00:00:00Z","timestamp":1412726400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2014,10,8]]},"DOI":"10.1145\/2659787.2659825","type":"proceedings-article","created":{"date-parts":[[2014,10,1]],"date-time":"2014-10-01T13:35:08Z","timestamp":1412170508000},"page":"87-96","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["A Compiler Optimization to Increase the Efficiency of WCET Analysis"],"prefix":"10.1145","author":[{"given":"Mohamed Abdel","family":"Maksoud","sequence":"first","affiliation":[{"name":"Compiler Research Group, Saarland University"}]},{"given":"Jan","family":"Reineke","sequence":"additional","affiliation":[{"name":"Real-Time and Embedded Systems Lab, Saarland University"}]}],"member":"320","published-online":{"date-parts":[[2014,10,8]]},"reference":[{"unstructured":"COIN-OR Linear Programming. http:\/\/www.coin-or.org\/Clp  COIN-OR Linear Programming. http:\/\/www.coin-or.org\/Clp","key":"e_1_3_2_1_1_1"},{"unstructured":"AbsInt Angewandte Informatik GmbH. AbsInt Advanced Analyzer for PowerPC MPC7448 (Simple Memory Model): User Documentation. http:\/\/www.absint.com\/ait\/mpc7448.htm  AbsInt Angewandte Informatik GmbH. AbsInt Advanced Analyzer for PowerPC MPC7448 (Simple Memory Model): User Documentation. http:\/\/www.absint.com\/ait\/mpc7448.htm","key":"e_1_3_2_1_2_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_3_1","DOI":"10.1145\/512950.512973"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_4_1","DOI":"10.1145\/2435227.2435236"},{"unstructured":"F. L. Drake and G. Rossum. The Python Language Reference Manual. Network theory Ltd. 2011. http:\/\/www.worldcat.org\/isbn\/9781906966140   F. L. Drake and G. Rossum. The Python Language Reference Manual. Network theory Ltd. 2011. http:\/\/www.worldcat.org\/isbn\/9781906966140","key":"e_1_3_2_1_5_1"},{"volume-title":"Uppsala University","year":"2002","author":"Engblom J.","key":"e_1_3_2_1_6_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_7_1","DOI":"10.5555\/646662.699670"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_8_1","DOI":"10.1007\/s11241-010-9101-x"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_9_1","DOI":"10.5555\/646787.703893"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_10_1","DOI":"10.1023\/A:1008186323068"},{"unstructured":"Free Software Foundation. GNU GCC Manual 2005. http:\/\/gcc.gnu.org\/onlinedocs\/gcc-4.0.0\/gcc\/  Free Software Foundation. GNU GCC Manual 2005. http:\/\/gcc.gnu.org\/onlinedocs\/gcc-4.0.0\/gcc\/","key":"e_1_3_2_1_11_1"},{"unstructured":"Freescale Semiconductor. MPC7450 RISC Microprocessor Family Reference Manual  Freescale Semiconductor. MPC7450 RISC Microprocessor Family Reference Manual","key":"e_1_3_2_1_12_1"},{"unstructured":"Freescale Semiconductor. Programming Environments Manual for 32-Bit Implementations of the PowerPCTM Architecture 2005. http:\/\/www.freescale.com\/files\/product\/doc\/MPCFPE32B.pdf  Freescale Semiconductor. Programming Environments Manual for 32-Bit Implementations of the PowerPCTM Architecture 2005. http:\/\/www.freescale.com\/files\/product\/doc\/MPCFPE32B.pdf","key":"e_1_3_2_1_13_1"},{"unstructured":"J. Gustafsson A. Betts A. Ermedahl and B. Lisper. The M\u00e4lardalen WCET benchmarks -- past present and future. pages 137--147 Brussels Belgium July 2010. OCG. http:\/\/dx.doi.org\/10.4230\/OASIcs.WCET.2010.136  J. Gustafsson A. Betts A. Ermedahl and B. Lisper. The M\u00e4lardalen WCET benchmarks -- past present and future. pages 137--147 Brussels Belgium July 2010. OCG. http:\/\/dx.doi.org\/10.4230\/OASIcs.WCET.2010.136","key":"e_1_3_2_1_14_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_15_1","DOI":"10.1023\/A:1008189014032"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_16_1","DOI":"10.1109\/JPROC.2003.814618"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_17_1","DOI":"10.1145\/217474.217570"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_18_1","DOI":"10.1109\/ICCD.2012.6378622"},{"unstructured":"M. A.\n       \n      Maksoud\n     and \n      \n      \n      J.\n       \n      Reineke\n      \n  \n  . \n  An empirical evaluation of the influence of the load-store unit on WCET analysis. In T. Vardanega editor 12th International Workshop on Worst-Case Execution Time Analysis volume \n  23\n   of \n  OpenAccess Series in Informatics (OASIcs) pages \n  13\n  --\n  24 Dagstuhl Germany 2012\n  . Schloss Dagstuhl--Leibniz-Zentrum fuer \n  Informatik\n  . http:\/\/dx.doi.org\/10.4230\/OASIcs.WCET.2012.13  M. A. Maksoud and J. Reineke. An empirical evaluation of the influence of the load-store unit on WCET analysis. In T. Vardanega editor 12th International Workshop on Worst-Case Execution Time Analysis volume 23 of OpenAccess Series in Informatics (OASIcs) pages 13--24 Dagstuhl Germany 2012. Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik. http:\/\/dx.doi.org\/10.4230\/OASIcs.WCET.2012.13","key":"e_1_3_2_1_19_1"},{"volume-title":"Proceedings of 6th International Workshop on Worst-Case Execution Time (WCET) Analysis","year":"2006","author":"Reineke J.","key":"e_1_3_2_1_20_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_21_1","DOI":"10.1145\/1062261.1062312"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"crossref","first-page":"346","DOI":"10.1007\/978-3-540-39962-9_43","volume-title":"On the Move to Meaningful Internet Systems 2003: Workshop on Java Technologies for Real-Time and Embedded Systems (JTRES","author":"Schoeberl M.","year":"2003"},{"key":"e_1_3_2_1_23_1","series-title":"OpenAccess Series in Informatics (OASIcs)","volume-title":"7th International Workshop on Worst-Case Execution Time Analysis (WCET'07)","author":"Stein I.","year":"2007"},{"volume-title":"Saarland University","year":"2002","author":"Theiling H.","key":"e_1_3_2_1_24_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_25_1","DOI":"10.5555\/646788.704041"},{"volume-title":"Saarland University","year":"2004","author":"Thesing S.","key":"e_1_3_2_1_26_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_27_1","DOI":"10.1109\/DSN.2003.1209972"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_28_1","DOI":"10.1023\/B:TIME.0000045316.66276.6e"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_29_1","DOI":"10.1109\/TCAD.2009.2013287"}],"event":{"sponsor":["CEA Commissariat \u00e0 l'\u00e9nergie atomique et aux \u00e9nergies alternatives","GDR ASR GDR Architecture, Syst\u00e8mes et R\u00e9seaux"],"acronym":"RTNS '14","name":"RTNS '14: 22nd International Conference on Real-Time Networks and Systems","location":"Versaille France"},"container-title":["Proceedings of the 22nd International Conference on Real-Time Networks and Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2659787.2659825","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2659787.2659825","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T07:19:47Z","timestamp":1750231187000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2659787.2659825"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,10,8]]},"references-count":29,"alternative-id":["10.1145\/2659787.2659825","10.1145\/2659787"],"URL":"https:\/\/doi.org\/10.1145\/2659787.2659825","relation":{},"subject":[],"published":{"date-parts":[[2014,10,8]]},"assertion":[{"value":"2014-10-08","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}