{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:49:20Z","timestamp":1750308560136,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":15,"publisher":"ACM","license":[{"start":{"date-parts":[[2014,9,1]],"date-time":"2014-09-01T00:00:00Z","timestamp":1409529600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2014,9]]},"DOI":"10.1145\/2660540.2661009","type":"proceedings-article","created":{"date-parts":[[2014,10,31]],"date-time":"2014-10-31T19:32:56Z","timestamp":1414783976000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Exploring Independent Gates in FinFET-Based Transistor Network Generation"],"prefix":"10.1145","author":[{"given":"Vinicius N.","family":"Possani","sequence":"first","affiliation":[{"name":"Technology Development Center, Federal University of Pelotas, Pelotas, Brazil"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andr\u00e9 I.","family":"Reis","sequence":"additional","affiliation":[{"name":"Institute of Informatics, Federal University of Rio Grande do Sul, Porto Alegre, Brazil"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Renato P.","family":"Ribas","sequence":"additional","affiliation":[{"name":"Institute of Informatics, Federal University of Rio Grande do Sul, Porto Alegre, Brazil"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Felipe S.","family":"Marques","sequence":"additional","affiliation":[{"name":"Technology Development Center, Federal University of Pelotas, Pelotas, Brazil"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Leomar S.","family":"da Rosa Junior","sequence":"additional","affiliation":[{"name":"Technology Development Center, Federal University of Pelotas, Pelotas, Brazil"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2014,9]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.915374"},{"key":"e_1_3_2_1_2_1","volume-title":"Technical Digest. International Electron Devices Meeting (IEDM '99)","author":"Huang X.","year":"1999","unstructured":"Huang , X. , Lee , W. , Kuo , C. , Hisamoto , D. , Chang , L. , Kedzierski , J. , Anderson , E. , Takeuchi , H. , Choi , Y. , Asano , K. , Subramanian , V. , King , T. , Bokor , J. , Hu , C. 1999 . Sub 50-nm FinFET: PMOS . Technical Digest. International Electron Devices Meeting (IEDM '99) , 67--70. Huang, X., Lee, W., Kuo, C., Hisamoto, D., Chang, L., Kedzierski, J., Anderson, E., Takeuchi, H., Choi, Y., Asano, K., Subramanian, V., King, T., Bokor, J., Hu, C. 1999. Sub 50-nm FinFET: PMOS. Technical Digest. International Electron Devices Meeting (IEDM '99), 67--70."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCD.2004.1263404"},{"key":"e_1_3_2_1_4_1","volume-title":"Proc. IEEE Int. Conf. on CAD (ICCAD","author":"Roy K.","year":"2005","unstructured":"Roy , K. , Mahmoodi , H. , Mukhopadhyay , S. , Anathan , H. , Bansal , A. and Cakici , T . 2005. Double-gate SOI devices for low-power and high-performance applications . in Proc. IEEE Int. Conf. on CAD (ICCAD 2005 ), 217--224. Roy, K., Mahmoodi, H., Mukhopadhyay, S., Anathan, H., Bansal, A. and Cakici, T. 2005. Double-gate SOI devices for low-power and high-performance applications. in Proc. IEEE Int. Conf. on CAD (ICCAD 2005), 217--224."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2005.856191"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.896320"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2007.4601953"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.881052"},{"key":"e_1_3_2_1_9_1","first-page":"1","article-title":"Independent-Gate FinFET Circuit Design Methodology","volume":"37","author":"Wang M. C.","year":"2010","unstructured":"Wang , M. C. 2010 . Independent-Gate FinFET Circuit Design Methodology . International Journal of Computer Science , 37 , 1 (Mar. 2010), 50. Wang, M. C. 2010. Independent-Gate FinFET Circuit Design Methodology. International Journal of Computer Science, 37, 1 (Mar. 2010), 50.","journal-title":"International Journal of Computer Science"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2097310"},{"key":"e_1_3_2_1_11_1","volume-title":"Boolean Factoring with Multi-Objective Goals. IEEE Int. Conf. on Computer Design (ICCD","author":"Martins M. G. A.","year":"2010","unstructured":"Martins , M. G. A. , Da Rosa Junior , L. S. , Rasmussen , A. , Ribas , R. P. and Reis , A. I . 2010 . Boolean Factoring with Multi-Objective Goals. IEEE Int. Conf. on Computer Design (ICCD 2010 ), 229--234. Martins, M. G. A., Da Rosa Junior, L. S., Rasmussen, A., Ribas, R. P. and Reis, A. I. 2010. Boolean Factoring with Multi-Objective Goals. IEEE Int. Conf. on Computer Design (ICCD 2010), 229--234."},{"key":"e_1_3_2_1_12_1","volume-title":"26th Symp. on Integrated Circuits and Systems Design (SBCCI","author":"Possani V. N.","year":"2013","unstructured":"Possani , V. N. , Callegaro , V. , Reis , A. I. , Ribas , R. P. , Marques , F. S. and Da Rosa Junior, L. S. 2013. Improving the Methodology to Build Non-Series-Parallel Transistor Arrangements . 26th Symp. on Integrated Circuits and Systems Design (SBCCI 2013 ), 1--6. Possani, V. N., Callegaro, V., Reis, A. I., Ribas, R. P., Marques, F. S. and Da Rosa Junior, L. S. 2013. Improving the Methodology to Build Non-Series-Parallel Transistor Arrangements. 26th Symp. on Integrated Circuits and Systems Design (SBCCI 2013), 1--6."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.dam.2008.02.011"},{"key":"e_1_3_2_1_14_1","unstructured":"IWLS 2005 Benchmarks: http:\/\/www.iwls.org.  IWLS 2005 Benchmarks: http:\/\/www.iwls.org."},{"key":"e_1_3_2_1_15_1","unstructured":"Berkeley Logic Synthesis and Verification Group ABC: A System for Sequential Synthesis and Verification Release 130115.  Berkeley Logic Synthesis and Verification Group ABC: A System for Sequential Synthesis and Verification Release 130115."}],"event":{"name":"SBCCI '14: 27th Symposium on Integrated Circuits and Systems Design","sponsor":["IEEE ICAS","SBC Brazilian Computer Society","IEEE Circuits and Systems Society","SIGDA ACM Special Interest Group on Design Automation","SBMICRO Brazilian Microelectronics Society"],"location":"Aracaju Brazil","acronym":"SBCCI '14"},"container-title":["Proceedings of the 27th Symposium on Integrated Circuits and Systems Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2660540.2661009","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2660540.2661009","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T19:04:05Z","timestamp":1750273445000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2660540.2661009"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,9]]},"references-count":15,"alternative-id":["10.1145\/2660540.2661009","10.1145\/2660540"],"URL":"https:\/\/doi.org\/10.1145\/2660540.2661009","relation":{},"subject":[],"published":{"date-parts":[[2014,9]]},"assertion":[{"value":"2014-09-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}