{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:52:16Z","timestamp":1759146736103,"version":"3.41.0"},"reference-count":47,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2015,2,17]],"date-time":"2015-02-17T00:00:00Z","timestamp":1424131200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"European Social Fund within the framework of realizing the project \"Support of Inter-sectoral Mobility and Quality Enhancement of Research Teams at Czech Technical University in Prague,\" CZ.1.07\/2.3.00\/30.0034"},{"name":"EU FP7 288008 T-CREST and 288248 Flextiles, CA505 BENEFIC, CA703 OpenES, ARTEMIS-2013-1 621429 EMC2, and 621353 DEWI"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2015,3,25]]},"abstract":"<jats:p>Ever-increasing demands for main memory bandwidth and memory speed\/power tradeoff led to the introduction of memories with multiple memory channels, such as Wide IO DRAM. Efficient utilization of a multichannel memory as a shared resource in multiprocessor real-time systems depends on mapping of the memory clients to the memory channels according to their requirements on latency, bandwidth, communication, and memory capacity. However, there is currently no real-time memory controller for multichannel memories, and there is no methodology to optimally configure multichannel memories in real-time systems. As a first work toward this direction, we present two main contributions in this article: (1) a configurable real-time multichannel memory controller architecture with a novel method for logical-to-physical address translation and (2) two design-time methods to map memory clients to the memory channels, one an optimal algorithm based on an integer programming formulation of the mapping problem, and the other a fast heuristic algorithm. We demonstrate the real-time guarantees on bandwidth and latency provided by our multichannel memory controller architecture by experimental evaluation. Furthermore, we compare the performance of the mapping problem formulation in a solver and the heuristic algorithm against two existing mapping algorithms in terms of computation time and mapping success ratio. We show that an optimal solution can be found in 2 hours using the solver and in less than 1 second with less than 7% mapping failure using the heuristic for realistically sized problems. Finally, we demonstrate configuring a Wide IO DRAM in a high-definition (HD) video and graphics processing system to emphasize the practical applicability and effectiveness of this work.<\/jats:p>","DOI":"10.1145\/2661635","type":"journal-article","created":{"date-parts":[[2015,2,18]],"date-time":"2015-02-18T13:24:05Z","timestamp":1424265845000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["A Real-Time Multichannel Memory Controller and Optimal Mapping of Memory Clients to Memory Channels"],"prefix":"10.1145","volume":"14","author":[{"given":"Manil Dev","family":"Gomony","sequence":"first","affiliation":[{"name":"Eindhoven University of Technology, The Netherlands"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Benny","family":"Akesson","sequence":"additional","affiliation":[{"name":"Czech Technical University in Prague, Czech Republic"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kees","family":"Goossens","sequence":"additional","affiliation":[{"name":"Eindhoven University of Technology, The Netherlands"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,2,17]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE'09)","author":"Aho E.","year":"2009","unstructured":"E. Aho , J. Nikara , P. A. Tuominen , and K. Kuusilinna . 2009. A case for multi-channel memories in video recording . In Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE'09) . 934--939. DOI:http:\/\/dx.doi.org\/10.1109\/DATE. 2009 .5090799 10.1109\/DATE.2009.5090799 E. Aho, J. Nikara, P. A. Tuominen, and K. Kuusilinna. 2009. A case for multi-channel memories in video recording. In Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE'09). 934--939. DOI:http:\/\/dx.doi.org\/10.1109\/DATE.2009.5090799"},{"key":"e_1_2_1_2_1","volume-title":"Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE'11)","author":"Akesson B.","year":"2011","unstructured":"B. Akesson and K. Goossens . 2011a. Architectures and modeling of predictable memory controllers for improved system integration . In Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE'11) . 1--6. DOI:http:\/\/dx.doi.org\/10.1109\/DATE. 2011 .5763145 10.1109\/DATE.2011.5763145 B. Akesson and K. Goossens. 2011a. Architectures and modeling of predictable memory controllers for improved system integration. In Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE'11). 1--6. DOI:http:\/\/dx.doi.org\/10.1109\/DATE.2011.5763145"},{"key":"e_1_2_1_3_1","doi-asserted-by":"crossref","unstructured":"B. Akesson and K. Goossens. 2011b. Memory Controllers for Real-Time Embedded Systems. Springer.   B. Akesson and K. Goossens. 2011b. Memory Controllers for Real-Time Embedded Systems. Springer.","DOI":"10.1007\/978-1-4419-8207-0"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTCSA.2008.21"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854314"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2012.05.007"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/SPL.2011.5782638"},{"key":"e_1_2_1_8_1","unstructured":"C. Bouquet. 2000. Optimal Multi-channel Memory Controller System. Patent number: 6643746.  C. Bouquet. 2000. Optimal Multi-channel Memory Controller System. Patent number: 6643746."},{"key":"e_1_2_1_9_1","volume-title":"Proceedings of the International Conference on Embedded Computer Systems (SAMOS'10)","author":"Cabarcas F.","year":"2010","unstructured":"F. Cabarcas , A. Rico , Y. Etsion , and A. Ramirez . 2010. Interleaving granularity on high bandwidth memory architecture for CMPs . In Proceedings of the International Conference on Embedded Computer Systems (SAMOS'10) . 250--257. DOI:http:\/\/dx.doi.org\/10.1109\/ICSAMOS. 2010 .5642060 10.1109\/ICSAMOS.2010.5642060 F. Cabarcas, A. Rico, Y. Etsion, and A. Ramirez. 2010. Interleaving granularity on high bandwidth memory architecture for CMPs. In Proceedings of the International Conference on Embedded Computer Systems (SAMOS'10). 250--257. DOI:http:\/\/dx.doi.org\/10.1109\/ICSAMOS.2010.5642060"},{"volume-title":"SoC Architecture to Multichannel Memory Management Using Sonics IMT. White paper. Sonics","author":"Casini P.","key":"e_1_2_1_10_1","unstructured":"P. Casini . 2008. SoC Architecture to Multichannel Memory Management Using Sonics IMT. White paper. Sonics , Inc . P. Casini. 2008. SoC Architecture to Multichannel Memory Management Using Sonics IMT. White paper. Sonics, Inc."},{"key":"e_1_2_1_11_1","unstructured":"CPLEX. 2014. IBM ILOG CPLEX Optimizer. Retrieved http:\/\/www.ibm.com.  CPLEX. 2014. IBM ILOG CPLEX Optimizer. Retrieved http:\/\/www.ibm.com."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/18.61110"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/2485288.2485602"},{"key":"e_1_2_1_14_1","volume-title":"Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE'12)","author":"Gomony M. D.","year":"2012","unstructured":"M. D. Gomony , C. Weis , B. Akesson , N. Wehn , and K. Goossens . 2012. DRAM selection and configuration for real-time mobile systems . In Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE'12) . 51--56. DOI:http:\/\/dx.doi.org\/10.1109\/DATE. 2012 .6176432 10.1109\/DATE.2012.6176432 M. D. Gomony, C. Weis, B. Akesson, N. Wehn, and K. Goossens. 2012. DRAM selection and configuration for real-time mobile systems. In Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE'12). 51--56. DOI:http:\/\/dx.doi.org\/10.1109\/DATE.2012.6176432"},{"volume-title":"Proceedings of the International Conference on Hardware\/Software Codesign and System Synthesis (CODES+ISSS'13)","author":"Goossens S.","key":"e_1_2_1_15_1","unstructured":"S. Goossens , J. Kuijsten , B. Akesson , and K. Goossens . 2013. A reconfigurable real-time SDRAM controller for mixed time-criticality systems . In Proceedings of the International Conference on Hardware\/Software Codesign and System Synthesis (CODES+ISSS'13) . S. Goossens, J. Kuijsten, B. Akesson, and K. Goossens. 2013. A reconfigurable real-time SDRAM controller for mixed time-criticality systems. In Proceedings of the International Conference on Hardware\/Software Codesign and System Synthesis (CODES+ISSS'13)."},{"key":"e_1_2_1_16_1","unstructured":"HMC. 2014. Homepage. Retrieved from http:\/\/www.hybridmemorycube.org.  HMC. 2014. Homepage. Retrieved from http:\/\/www.hybridmemorycube.org."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/SIPS.2007.4387575"},{"key":"e_1_2_1_18_1","unstructured":"JEDEC. 2014. Wide I\/O Single Data Rate Specification. Retrieved from http:\/\/www.jedec.org.  JEDEC. 2014. Wide I\/O Single Data Rate Specification. Retrieved from http:\/\/www.jedec.org."},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/49.105173"},{"volume-title":"Proceedings of the IEEE Real-Time Technology and Applications Symposium (RTAS'14)","author":"Kim H.","key":"e_1_2_1_20_1","unstructured":"H. Kim , D. de Niz , B. Andersson , M. Klein , O. Mutlu , and R. Rajkumar . 2014. Bounding memory interference delay in COTS-based multicore systems . In Proceedings of the IEEE Real-Time Technology and Applications Symposium (RTAS'14) . H. Kim, D. de Niz, B. Andersson, M. Klein, O. Mutlu, and R. Rajkumar. 2014. Bounding memory interference delay in COTS-based multicore systems. In Proceedings of the IEEE Real-Time Technology and Applications Symposium (RTAS'14)."},{"volume-title":"Proceedings of the Conference on Design, Automation and Test in Europe (DATE'09)","author":"Kollig P.","key":"e_1_2_1_21_1","unstructured":"P. Kollig , C. Osborne , and T. Henriksson . 2009. Heterogeneous multi-core platform for consumer multimedia applications . In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'09) . 1254--1259. P. Kollig, C. Osborne, and T. Henriksson. 2009. Heterogeneous multi-core platform for consumer multimedia applications. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'09). 1254--1259."},{"key":"e_1_2_1_22_1","volume-title":"Proceedings of the 30th Annual IEEE\/ACM International Symposium on Microarchitecture. 330--335","author":"Lee C.","year":"1997","unstructured":"C. Lee , M. Potkonjak , and W. H. Mangione-Smith . 1997. MediaBench: A tool for evaluating and synthesizing multimedia and communications systems . In Proceedings of the 30th Annual IEEE\/ACM International Symposium on Microarchitecture. 330--335 . DOI:http:\/\/dx.doi.org\/10.1109\/MICRO. 1997 .645830 10.1109\/MICRO.1997.645830 C. Lee, M. Potkonjak, and W. H. Mangione-Smith. 1997. MediaBench: A tool for evaluating and synthesizing multimedia and communications systems. In Proceedings of the 30th Annual IEEE\/ACM International Symposium on Microarchitecture. 330--335. DOI:http:\/\/dx.doi.org\/10.1109\/MICRO.1997.645830"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2014.18"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2005.26"},{"key":"e_1_2_1_25_1","volume-title":"Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE'10)","author":"Loi I.","year":"2010","unstructured":"I. Loi and L. Benini . 2010. An efficient distributed memory interface for many-core platform with 3D stacked DRAM . In Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE'10) . 99--104. DOI:http:\/\/dx.doi.org\/10.1109\/DATE. 2010 .5457230 10.1109\/DATE.2010.5457230 I. Loi and L. Benini. 2010. An efficient distributed memory interface for many-core platform with 3D stacked DRAM. In Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE'10). 99--104. DOI:http:\/\/dx.doi.org\/10.1109\/DATE.2010.5457230"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228568"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.5555\/1736530.1736556"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/ChinaGrid.2011.29"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/2435227.2435260"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/2039370.2039388"},{"key":"e_1_2_1_31_1","volume-title":"Proceedings of the 2010 IEEE International Symposium on Parallel Distributed Processing, Workshops and Phd Forum (IPDPSW'10)","author":"Sancho J. C.","year":"2010","unstructured":"J. C. Sancho , M. Lang , and D. K. Kerbyson . 2010. Analyzing the trade-off between multiple memory controllers and memory channels on multi-core processor performance . In Proceedings of the 2010 IEEE International Symposium on Parallel Distributed Processing, Workshops and Phd Forum (IPDPSW'10) . 1--7. DOI:http:\/\/dx.doi.org\/10.1109\/IPDPSW. 2010 .5470812 10.1109\/IPDPSW.2010.5470812 J. C. Sancho, M. Lang, and D. K. Kerbyson. 2010. Analyzing the trade-off between multiple memory controllers and memory channels on multi-core processor performance. In Proceedings of the 2010 IEEE International Symposium on Parallel Distributed Processing, Workshops and Phd Forum (IPDPSW'10). 1--7. DOI:http:\/\/dx.doi.org\/10.1109\/IPDPSW.2010.5470812"},{"key":"e_1_2_1_32_1","volume-title":"Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE'12)","author":"Shah H.","year":"2012","unstructured":"H. Shah , A. Raabe , and A. Knoll . 2012. Bounding WCET of applications using SDRAM with priority based budget scheduling in MPSoCs . In Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE'12) . 665--670. DOI:http:\/\/dx.doi.org\/10.1109\/DATE. 2012 .6176554 10.1109\/DATE.2012.6176554 H. Shah, A. Raabe, and A. Knoll. 2012. Bounding WCET of applications using SDRAM with priority based budget scheduling in MPSoCs. In Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE'12). 665--670. DOI:http:\/\/dx.doi.org\/10.1109\/DATE.2012.6176554"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/90.502236"},{"key":"e_1_2_1_34_1","unstructured":"SimpleScalar. 2004. Homepage. Retrieved from http:\/\/www.simplescalar.com.  SimpleScalar. 2004. Homepage. Retrieved from http:\/\/www.simplescalar.com."},{"key":"e_1_2_1_35_1","volume-title":"Embedded Multiprocessors: Scheduling and Synchronization","author":"Sriram S.","year":"2000","unstructured":"S. Sriram and S. S. Bhattacharyya . 2000 . Embedded Multiprocessors: Scheduling and Synchronization . Marcel Dekker, New York , NY. S. Sriram and S. S. Bhattacharyya. 2000. Embedded Multiprocessors: Scheduling and Synchronization. Marcel Dekker, New York, NY."},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2008.36"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2009.148"},{"key":"e_1_2_1_38_1","unstructured":"A. Stevens. 2010. QoS for High-Performance and Power-Efficient HD Multimedia. ARM White paper. Retrieved from http:\/\/wwww.arm.com.  A. Stevens. 2010. QoS for High-Performance and Power-Efficient HD Multimedia. ARM White paper. Retrieved from http:\/\/wwww.arm.com."},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/90.731196"},{"key":"e_1_2_1_40_1","unstructured":"Texas Instruments Inc. 2014. TMS320VC5505\/5504 DSP Direct Memory Access (DMA) Controller. Retrieved from http:\/\/www.ti.com.  Texas Instruments Inc. 2014. TMS320VC5505\/5504 DSP Direct Memory Access (DMA) Controller. Retrieved from http:\/\/www.ti.com."},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.5555\/1874620.1874924"},{"key":"e_1_2_1_42_1","volume-title":"Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE'11)","author":"van der Wolf P.","year":"2011","unstructured":"P. van der Wolf and J. Geuzebroek . 2011. SoC infrastructures for predictable system integration . In Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE'11) . 1--6. DOI:http:\/\/dx.doi.org\/10.1109\/DATE. 2011 .5763146 10.1109\/DATE.2011.5763146 P. van der Wolf and J. Geuzebroek. 2011. SoC infrastructures for predictable system integration. In Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE'11). 1--6. DOI:http:\/\/dx.doi.org\/10.1109\/DATE.2011.5763146"},{"key":"e_1_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2013.44"},{"key":"e_1_2_1_44_1","unstructured":"Xilinx Inc. 2014. LogiCORE IP XPS Multi-channel External Memory Controller (XPS MCH EMC). Retrieved from http:\/\/www.xilinx.com.  Xilinx Inc. 2014. LogiCORE IP XPS Multi-channel External Memory Controller (XPS MCH EMC). Retrieved from http:\/\/www.xilinx.com."},{"key":"e_1_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228517"},{"key":"e_1_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2010.5751446"},{"key":"e_1_2_1_47_1","volume-title":"Proceedings of the 8th International Symposium on High-Performance Computer Architecture. 107--116","author":"Zhu Z.","year":"2002","unstructured":"Z. Zhu , Z. Zhang , and X. Zhang . 2002. Fine-grain priority scheduling on multi-channel memory systems . In Proceedings of the 8th International Symposium on High-Performance Computer Architecture. 107--116 . DOI:http:\/\/dx.doi.org\/10.1109\/HPCA. 2002 .995702 10.1109\/HPCA.2002.995702 Z. Zhu, Z. Zhang, and X. Zhang. 2002. Fine-grain priority scheduling on multi-channel memory systems. In Proceedings of the 8th International Symposium on High-Performance Computer Architecture. 107--116. DOI:http:\/\/dx.doi.org\/10.1109\/HPCA.2002.995702"}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2661635","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2661635","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T07:28:15Z","timestamp":1750231695000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2661635"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,2,17]]},"references-count":47,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2015,3,25]]}},"alternative-id":["10.1145\/2661635"],"URL":"https:\/\/doi.org\/10.1145\/2661635","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"type":"print","value":"1539-9087"},{"type":"electronic","value":"1558-3465"}],"subject":[],"published":{"date-parts":[[2015,2,17]]},"assertion":[{"value":"2013-06-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2014-08-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2015-02-17","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}