{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:18:33Z","timestamp":1750306713776,"version":"3.41.0"},"reference-count":1,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2014,9,17]],"date-time":"2014-09-17T00:00:00Z","timestamp":1410912000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGACT News"],"published-print":{"date-parts":[[2014,9,17]]},"abstract":"<jats:p>We describe the problem of inferring a set of memory map instructions from a reference trace, with the goal of minimizing the number of such instructions as well as the number of unreferenced but mapped storage locations. We prove the related decision problem NP-complete. We then present and compare the results of two heuristic approaches on some actual traces.<\/jats:p>","DOI":"10.1145\/2670418.2670433","type":"journal-article","created":{"date-parts":[[2014,9,19]],"date-time":"2014-09-19T12:27:17Z","timestamp":1411129637000},"page":"47-52","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Inferring memory map instructions"],"prefix":"10.1145","volume":"45","author":[{"given":"Paul T.","family":"Scheid","sequence":"first","affiliation":[{"name":"Washington University"}]},{"given":"Ari J.","family":"Spilo","sequence":"additional","affiliation":[{"name":"Washington University"}]},{"given":"Ron K.","family":"Cytron","sequence":"additional","affiliation":[{"name":"Washington University"}]}],"member":"320","published-online":{"date-parts":[[2014,9,17]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Proceedings of the 5th Annual Workshop on Modeling, Benchmarking and Simulation","author":"Bienia Christian","year":"2009","unstructured":"Christian Bienia and Kai Li. Parsec 2.0 : A new benchmark suite for chip-multiprocessors . In Proceedings of the 5th Annual Workshop on Modeling, Benchmarking and Simulation , June 2009 . Christian Bienia and Kai Li. Parsec 2.0: A new benchmark suite for chip-multiprocessors. In Proceedings of the 5th Annual Workshop on Modeling, Benchmarking and Simulation, June 2009."}],"container-title":["ACM SIGACT News"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2670418.2670433","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2670418.2670433","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T07:19:20Z","timestamp":1750231160000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2670418.2670433"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,9,17]]},"references-count":1,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2014,9,17]]}},"alternative-id":["10.1145\/2670418.2670433"],"URL":"https:\/\/doi.org\/10.1145\/2670418.2670433","relation":{},"ISSN":["0163-5700"],"issn-type":[{"type":"print","value":"0163-5700"}],"subject":[],"published":{"date-parts":[[2014,9,17]]},"assertion":[{"value":"2014-09-17","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}