{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:16:47Z","timestamp":1750306607629,"version":"3.41.0"},"reference-count":23,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2015,3,2]],"date-time":"2015-03-02T00:00:00Z","timestamp":1425254400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2015,3,2]]},"abstract":"<jats:p>Testing analog integrated circuits is expensive in terms of both test equipment and time. To reduce the cost, Design-For-Test techniques (DFT) such as Built-In Self-Test (BIST) have been developed. For a given Circuit Under Test (CUT), the choice of a suitable technique should be made at the design stage as a result of the analysis of test metrics such as test escapes and yield loss. However, it is very hard to carry out this estimation for analog\/RF circuits by using fault simulation techniques. Instead, the estimation of parametric test metrics is made possible by Monte Carlo circuit-level simulations and the construction of statistical models. These models represent the output parameter space of the CUT in which the test metrics are defined. In addition, models of the input parameter space may be required to accelerate the simulations and obtain higher confidence in the DFT choices. In this work, we describe a methodological flow for the selection of most adequate statistical models and several techniques that can be used for obtaining these models. Some of these techniques have been integrated into a Computer-Aided Test (CAT) tool for the automation of the process of test metrics estimation. This estimation is illustrated for the case of a BIST solution for CMOS imager pixels that requires the use of advanced statistical modeling techniques.<\/jats:p>","DOI":"10.1145\/2699837","type":"journal-article","created":{"date-parts":[[2015,3,3]],"date-time":"2015-03-03T14:08:19Z","timestamp":1425391699000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["A Tool for Analog\/RF BIST Evaluation Using Statistical Models of Circuit Parameters"],"prefix":"10.1145","volume":"20","author":[{"given":"Kamel","family":"Beznia","sequence":"first","affiliation":[{"name":"University of Brest, Cedex, France"}]},{"given":"Ahcene","family":"Bounceur","sequence":"additional","affiliation":[{"name":"University of Brest, Cedex, France"}]},{"given":"Reinhardt","family":"Euler","sequence":"additional","affiliation":[{"name":"University of Brest, Cedex, France"}]},{"given":"Salvador","family":"Mir","sequence":"additional","affiliation":[{"name":"TIMA Laboratory, Grenoble Cedex, France"}]}],"member":"320","published-online":{"date-parts":[[2015,3,2]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF02613322"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/IMS3TW.2011.19"},{"volume-title":"Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems (ICECS'12)","author":"Beznia K.","key":"e_1_2_1_4_1","unstructured":"K. Beznia , A. Bounceur , S. Mir , and R. Euler . 2012. Accurate estimation of analog test metrics with extreme circuits . In Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems (ICECS'12) . 272--275. K. Beznia, A. Bounceur, S. Mir, and R. Euler. 2012. Accurate estimation of analog test metrics with extreme circuits. In Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems (ICECS'12). 272--275."},{"volume-title":"Proceedings of the 28th IEEE International Conference on Design of Circuits and Integrated Systems (DCIS'13)","author":"Beznia K.","key":"e_1_2_1_5_1","unstructured":"K. Beznia , A. Bounceur , S. Mir , and R. Euler . 2013a. Analog output parameter reduction based on test metrics estimation . In Proceedings of the 28th IEEE International Conference on Design of Circuits and Integrated Systems (DCIS'13) . K. Beznia, A. Bounceur, S. Mir, and R. Euler. 2013a. Analog output parameter reduction based on test metrics estimation. In Proceedings of the 28th IEEE International Conference on Design of Circuits and Integrated Systems (DCIS'13)."},{"volume-title":"Proceedings of the IEEE International Conference on Design Technology of Integrated Systems in Nanoscale Era (DTIS'13)","author":"Beznia K.","key":"e_1_2_1_6_1","unstructured":"K. Beznia , A. Bounceur , S. Mir , and R. Euler . 2013b. Statistical modelling of analog circuits for test metrics computation . In Proceedings of the IEEE International Conference on Design Technology of Integrated Systems in Nanoscale Era (DTIS'13) . 25--29. K. Beznia, A. Bounceur, S. Mir, and R. Euler. 2013b. Statistical modelling of analog circuits for test metrics computation. In Proceedings of the IEEE International Conference on Design Technology of Integrated Systems in Nanoscale Era (DTIS'13). 25--29."},{"key":"e_1_2_1_7_1","volume-title":"Proceedings of the 14th International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC'07)","volume":"249","author":"Bounceur A.","unstructured":"A. Bounceur , S. Mir , L. Rolindez , and E. Simeu . 2007a. CAT platform for analogue and mixed-signal test evaluation and optimization . In Proceedings of the 14th International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC'07) . Vol. 249 , Springer, 281--300. A. Bounceur, S. Mir, L. Rolindez, and E. Simeu. 2007a. CAT platform for analogue and mixed-signal test evaluation and optimization. In Proceedings of the 14th International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC'07). Vol. 249, Springer, 281--300."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-007-5006-6"},{"volume-title":"Proceedings of the 12th International Mixed-Signals Testing Workshop (IMSTW'06)","author":"Bounceur A.","key":"e_1_2_1_9_1","unstructured":"A. Bounceur , S. Mir , E. Simeu , and L. Rolindez . 2006. On the accurate estimation of test metrics for multiple analogue parametric deviations . In Proceedings of the 12th International Mixed-Signals Testing Workshop (IMSTW'06) . 19--26. A. Bounceur, S. Mir, E. Simeu, and L. Rolindez. 2006. On the accurate estimation of test metrics for multiple analogue parametric deviations. In Proceedings of the 12th International Mixed-Signals Testing Workshop (IMSTW'06). 19--26."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2149522"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1093\/biomet\/65.1.141"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1006\/jmva.1997.1672"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.2307\/3314660"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.insmatheco.2007.10.005"},{"volume-title":"Proceedings of the IEEE International Conference on Design Technology of Integrated Systems in Nanoscale Era (DTIS'13)","author":"Huang K.","key":"e_1_2_1_15_1","unstructured":"K. Huang , H.-G. Stratigopoulos , L. Abdallah , S. Mir , and A. Bounceur . 2013. Multivariate statistical techniques for analog parametric test metrics estimation . In Proceedings of the IEEE International Conference on Design Technology of Integrated Systems in Nanoscale Era (DTIS'13) . 6--11. K. Huang, H.-G. Stratigopoulos, L. Abdallah, S. Mir, and A. Bounceur. 2013. Multivariate statistical techniques for analog parametric test metrics estimation. In Proceedings of the IEEE International Conference on Design Technology of Integrated Systems in Nanoscale Era (DTIS'13). 6--11."},{"volume-title":"Proceedings of the 23rd International Conference on Design of Circuits and Integrated Systems (DCIS'08)","author":"Lechuga Y.","key":"e_1_2_1_16_1","unstructured":"Y. Lechuga , A. Bounceur , R. Mozuelos , M. Martinez , S. Bracho , and S. Mir . 2008. Test limits evaluation for an ADC design-for-test approach by using a CAT platform . In Proceedings of the 23rd International Conference on Design of Circuits and Integrated Systems (DCIS'08) . Y. Lechuga, A. Bounceur, R. Mozuelos, M. Martinez, S. Bracho, and S. Mir. 2008. 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