{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,1]],"date-time":"2026-04-01T20:01:59Z","timestamp":1775073719397,"version":"3.50.1"},"reference-count":72,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2015,3,2]],"date-time":"2015-03-02T00:00:00Z","timestamp":1425254400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2015,3,2]]},"abstract":"<jats:p>As the size and density of silicon chips continue to increase, maintaining acceptable manufacturing yields has become increasingly difficult. Recent works suggest that lithography techniques are reaching their limits with respect to enabling high yield fabrication of small-scale devices, thus there is an increasing need for techniques that can tolerate fabrication time defects. One candidate technology to help combat these defects is reconfigurable hardware. The flexible nature of reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs), makes it possible for them to route around defective areas of a chip after the device has been packaged and deployed into the field.<\/jats:p>\n          <jats:p>This work presents a technique that aims to increase the effective yield of FPGA manufacturing by re-claiming a portion of chips that would be ordinarily classified as unusable. In brief, we propose a modification to existing commercial toolchain flows to make them fault aware. A phase is added to identify faults within the chip. The locations of these faults are then used by the toolchain to avoid faults during the placement and routing phase.<\/jats:p>\n          <jats:p>Specifically, we have applied our approach to the Xilinx commercial toolchain flow and evaluated its tolerance to both logic and routing resource faults. Our findings show that, at a cost of 5--10% in device frequency performance, the modified toolchain flow can tolerate up to 30% of logic resources being faulty and, depending on the nature of the target application, can tolerate 1--30% of the device's routing resources being faulty. These results provide strong evidence that commercial toolchains not designed for the purpose of tolerating faults can still be greatly leveraged in the presence of faults to place and route circuits in an efficient manner.<\/jats:p>","DOI":"10.1145\/2699838","type":"journal-article","created":{"date-parts":[[2015,3,3]],"date-time":"2015-03-03T14:08:19Z","timestamp":1425391699000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["A Fault-Aware Toolchain Approach for FPGA Fault Tolerance"],"prefix":"10.1145","volume":"20","author":[{"given":"Adwait","family":"Gupte","sequence":"first","affiliation":[{"name":"Iowa State University, Ames, IA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sudhanshu","family":"Vyas","sequence":"additional","affiliation":[{"name":"Iowa State University, Ames, IA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Phillip H.","family":"Jones","sequence":"additional","affiliation":[{"name":"Iowa State University, Ames, IA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,3,2]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2442087.2442104"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2013.34"},{"key":"e_1_2_1_3_1","volume-title":"Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM'95)","author":"Amerson R."},{"key":"e_1_2_1_4_1","volume-title":"Proceedings of the International Conference on Field-Programmable Technology (FPT'12)","author":"Amouri A."},{"key":"e_1_2_1_5_1","volume-title":"Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL'12)","author":"Amouri A."},{"key":"e_1_2_1_6_1","volume-title":"Proceedings of the 23rd International Conference on Field Programmable Logic and Applications (FPL'13)","author":"Amouri A."},{"key":"e_1_2_1_7_1","doi-asserted-by":"crossref","unstructured":"A. Amouri and M. Tahoori. 2013b. Lifetime reliability sensing in modern FPGAs. In Embedded Systems Design with FPGAs P. Athanas D. Pnevmatikatos and N. Sklavos Eds. Springer 55--77.  A. Amouri and M. Tahoori. 2013b. Lifetime reliability sensing in modern FPGAs. In Embedded Systems Design with FPGAs P. Athanas D. Pnevmatikatos and N. Sklavos Eds. Springer 55--77.","DOI":"10.1007\/978-1-4614-1362-2_3"},{"key":"e_1_2_1_8_1","volume-title":"Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications (FPL'97)","author":"Betz V."},{"key":"e_1_2_1_9_1","volume-title":"Proceedings of the 7th International Conference on Control, Automation, Robotics and Vision (ICARCV'02)","volume":"3","author":"Bing X."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2005.1515827"},{"key":"e_1_2_1_11_1","volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'05)","author":"Campregher N."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1046192.1046211"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1142155.1142167"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/54.867894"},{"key":"e_1_2_1_15_1","volume-title":"Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM'96)","author":"Culbertson W."},{"key":"e_1_2_1_16_1","volume-title":"Proceedings of the 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'97)","author":"Culbertson W."},{"key":"e_1_2_1_17_1","volume-title":"Proceedings of the 12th International Conference on VLSI Design-VLSI for the Information Appliance (VLSID'99)","author":"Das D."},{"key":"e_1_2_1_18_1","volume-title":"Proceedings of the ACM International Workshop on Field Programmable Gate Arrays (ICVD'94)","author":"Durand S."},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2006.47"},{"key":"e_1_2_1_20_1","volume-title":"Proceedings of the 41st Southeastern Symposium on System Theory (SSST'09)","author":"Dutton B."},{"key":"e_1_2_1_21_1","volume-title":"Proceedings of the 41st Southeastern Symposium on System Theory (SSST'09)","author":"Dutton B."},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.891102"},{"key":"e_1_2_1_23_1","volume-title":"Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications (FPL'97)","author":"Emmert J. M."},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1972.1052898"},{"key":"e_1_2_1_25_1","volume-title":"Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'10). 1803","author":"Gupte A.","year":"1808"},{"key":"e_1_2_1_26_1","volume-title":"Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'96)","author":"Hanchek F."},{"key":"e_1_2_1_27_1","volume-title":"Proceedings of the IEEE Custom Integrated Circuits Conference (CICC'93)","author":"Hatori F."},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.273147"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2009.2013921"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.850090"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2013.40"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/54.655181"},{"key":"e_1_2_1_33_1","volume-title":"Proceedings of the 37th Asian Test Symposium (ATS'98)","author":"Itazaki N."},{"key":"e_1_2_1_34_1","unstructured":"ITRS. 2013a. The International Technology Roadmap for Semiconductors (ITRS) Interconnect. http:\/\/www.itrs.net\/.  ITRS. 2013a. The International Technology Roadmap for Semiconductors (ITRS) Interconnect. http:\/\/www.itrs.net\/."},{"key":"e_1_2_1_35_1","unstructured":"ITRS. 2013b. The International Technology Roadmap for Semiconductors (ITRS) Metrology. http:\/\/www.itrs.net\/.  ITRS. 2013b. The International Technology Roadmap for Semiconductors (ITRS) Metrology. http:\/\/www.itrs.net\/."},{"key":"e_1_2_1_36_1","unstructured":"ITRS. 2013c. The International Technology Roadmap for Semiconductors (ITRS) Yield Enhancement. http:\/\/www.itrs.net\/.  ITRS. 2013c. The International Technology Roadmap for Semiconductors (ITRS) Yield Enhancement. http:\/\/www.itrs.net\/."},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2040125"},{"key":"e_1_2_1_38_1","volume-title":"Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'94)","author":"Kelly J."},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2008.925937"},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/TSM.2005.852110"},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2002.804492"},{"key":"e_1_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2011.247"},{"key":"e_1_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2003.818545"},{"key":"e_1_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1971.223159"},{"key":"e_1_2_1_45_1","volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'06)","author":"Maidee P."},{"key":"e_1_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.1998.658762"},{"key":"e_1_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1109\/N-SSC.2006.4785860"},{"key":"e_1_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.298034"},{"key":"e_1_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2242100"},{"key":"e_1_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1967.264748"},{"key":"e_1_2_1_51_1","volume-title":"Proceedings of the 23rd International Conference on Field Programmable Logic and Applications (FPL'13)","author":"Rao P."},{"key":"e_1_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1145\/307418.307576"},{"key":"e_1_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1016\/S1369-7021(06)71790-4"},{"key":"e_1_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145708"},{"key":"e_1_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.475125"},{"key":"e_1_2_1_56_1","first-page":"801","article-title":"Insight into a generic interconnect resource model for Xilinx Virtex and Spartan series FPGAs","volume":"60","author":"Ruan A.","year":"2013","journal-title":"IEEE Trans. Circ. Syst. II: Express Briefs"},{"key":"e_1_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508133"},{"key":"e_1_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.276.0549"},{"key":"e_1_2_1_59_1","volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'08)","author":"Stott E."},{"key":"e_1_2_1_60_1","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2009.0011"},{"key":"e_1_2_1_61_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2010.88"},{"key":"e_1_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1145\/1723112.1723152"},{"key":"e_1_2_1_63_1","volume-title":"Proceedings of the International Test Conference (TEST'02)","author":"Stroud C."},{"key":"e_1_2_1_64_1","volume-title":"Proceedings of the International Test Conference (TEST'00)","author":"Sun X."},{"key":"e_1_2_1_65_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2056941"},{"key":"e_1_2_1_66_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.852452"},{"key":"e_1_2_1_67_1","volume-title":"Proceedings of the International Conference on Field-Programmable Technology (FPT'10)","author":"Tzilis S."},{"key":"e_1_2_1_68_1","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2008.23"},{"key":"e_1_2_1_69_1","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:19990532"},{"key":"e_1_2_1_70_1","volume-title":"Proceedings of the International Symposium on VLSI Technology, Systems and Applications (VTSA'99)","author":"Wu C.-F.","year":"1999"},{"key":"e_1_2_1_71_1","unstructured":"XILINX. 2011. Easypath-6 FPGA product brief. http:\/\/www.xilinx.com\/publications\/prod_mktg\/EasyPath6_Product_Brief.pdf.  XILINX. 2011. Easypath-6 FPGA product brief. http:\/\/www.xilinx.com\/publications\/prod_mktg\/EasyPath6_Product_Brief.pdf."},{"key":"e_1_2_1_72_1","unstructured":"XILINX. 2104. Virtex-5 FPGA datasheet. http:\/\/www.xilinx.com\/support\/documentation\/data_sheets\/ds202.pdf.  XILINX. 2104. Virtex-5 FPGA datasheet. http:\/\/www.xilinx.com\/support\/documentation\/data_sheets\/ds202.pdf."}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2699838","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2699838","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T06:16:59Z","timestamp":1750227419000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2699838"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,3,2]]},"references-count":72,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2015,3,2]]}},"alternative-id":["10.1145\/2699838"],"URL":"https:\/\/doi.org\/10.1145\/2699838","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"value":"1084-4309","type":"print"},{"value":"1557-7309","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,3,2]]},"assertion":[{"value":"2012-02-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2014-11-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2015-03-02","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}