{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T12:03:17Z","timestamp":1759147397158,"version":"3.41.0"},"reference-count":50,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2015,4,30]],"date-time":"2015-04-30T00:00:00Z","timestamp":1430352000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2015,5,21]]},"abstract":"<jats:p>Multiprocessor Systems-on-Chip (MPSoC) applications can rely today on a very large spectrum of interconnection topologies potentially meeting given communication requirements, determining various trade-offs between cost and performance. Building interconnects that enable concurrent communication tasks introduces decisive opportunities for reducing the overall communication latency. This work identifies three levels of parallelism at the interconnect level: global parallelism across different independent domains; local or intradomain parallelism, relying on inherently concurrent interconnect components such as crossbars; and interdomain parallelism, where multiple concurrent paths across different local domains are exploited. We propose an automated methodology to search the design space, aimed at maximizing the exploitation of these forms of parallelism. The approach also takes into consideration possible dependencies between communication tasks, which further constrains the design space, making the identification of a feasible solution more challenging. By jointly solving a scheduling and interconnect synthesis problem, the methodology turns the description of the application communication requirements, including data dependencies, into an on-chip synthesizable interconnection structure along with a communication schedule satisfying given area constraints. The article thoroughly describes the formalisms and the methodology used to derive such optimized heterogeneous topologies. It also discusses some case studies emphasizing the impact of the proposed approach and highlighting the essential differences with a few other solutions presented in the technical literature.<\/jats:p>","DOI":"10.1145\/2700075","type":"journal-article","created":{"date-parts":[[2015,5,1]],"date-time":"2015-05-01T17:49:08Z","timestamp":1430502548000},"page":"1-24","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":10,"title":["Exploiting Concurrency for the Automated Synthesis of MPSoC Interconnects"],"prefix":"10.1145","volume":"14","author":[{"given":"Alessandro","family":"Cilardo","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering and Information Technologies, University of Naples Federico II, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Edoardo","family":"Fusella","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering and Information Technologies, University of Naples Federico II, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luca","family":"Gallo","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering and Information Technologies, University of Naples Federico II, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Antonino","family":"Mazzeo","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering and Information Technologies, University of Naples Federico II, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,4,30]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"ARM Limited. 2008. AMBA Specification Rev 2.0. Retrieved from http:\/\/www.arm.com. ARM Limited. 2008. AMBA Specification Rev 2.0. Retrieved from http:\/\/www.arm.com."},{"key":"e_1_2_1_2_1","unstructured":"ARM. 2011. AMBA AXI and ACE Protocol Specification. ARM. 2011. AMBA AXI and ACE Protocol Specification."},{"key":"e_1_2_1_3_1","unstructured":"Arteris. 2009. From Bus and Crossbar to Network-On-Chip. White Paper. Arteris. 2009. From Bus and Crossbar to Network-On-Chip. White Paper."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/1018437.1021820"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2005.20"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.5555\/832285.835542"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2460239.2460244"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPAMI.1986.4767851"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645494"},{"key":"e_1_2_1_11_1","volume-title":"Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE)","author":"Cilardo Alessandro","year":"2014","unstructured":"Alessandro Cilardo , Edoardo Fusella , Luca Gallo , and Antonino Mazzeo . 2014 a. Joint communication scheduling and interconnect synthesis for FPGA-based many-core systems . In Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE) , 2014. IEEE. Alessandro Cilardo, Edoardo Fusella, Luca Gallo, and Antonino Mazzeo. 2014a. Joint communication scheduling and interconnect synthesis for FPGA-based many-core systems. In Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014. IEEE."},{"key":"e_1_2_1_12_1","doi-asserted-by":"crossref","unstructured":"A. Cilardo E. Fusella L. Gallo A. Mazzeo and N. Mazzocca. 2014b. Automated design space exploration for FPGA-based heterogeneous interconnects. Design Automation for Embedded Systems 1--14. A. Cilardo E. Fusella L. Gallo A. Mazzeo and N. Mazzocca. 2014b. Automated design space exploration for FPGA-based heterogeneous interconnects. Design Automation for Embedded Systems 1--14.","DOI":"10.7873\/DATE2014.352"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379048"},{"key":"e_1_2_1_14_1","unstructured":"Giovanni De Micheli and Luca Benini. 2006. Networks on Chips: Technology and Tools. Morgan Kaufmann. Giovanni De Micheli and Luca Benini. 2006. Networks on Chips: Technology and Tools. Morgan Kaufmann."},{"key":"e_1_2_1_15_1","volume-title":"Devanur and Uriel Feige","author":"Nikhil","year":"2011","unstructured":"Nikhil R. Devanur and Uriel Feige . 2011 . An O (n log n) algorithm for a load balancing problem on paths. In Algorithms and Data Structures. Springer , New York, 326--337. Nikhil R. Devanur and Uriel Feige. 2011. An O (n log n) algorithm for a load balancing problem on paths. In Algorithms and Data Structures. Springer, New York, 326--337."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.5555\/278241.278309"},{"volume-title":"National Bureau of Standards","author":"Edmonds Jack","key":"e_1_2_1_17_1","unstructured":"Jack Edmonds . 1968. Optimum Branchings . National Bureau of Standards , Gaithersburg, MD . Jack Edmonds. 1968. Optimum Branchings. National Bureau of Standards, Gaithersburg, MD."},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2026356"},{"key":"e_1_2_1_19_1","volume-title":"A unified approach to mapping and routing on a network-on-chip for both best-effort and guaranteed service traffic. VLSI Design","author":"Hansson Andreas","year":"2007","unstructured":"Andreas Hansson , Kees Goossens , and Andrei R\u0103dulescu . 2007. A unified approach to mapping and routing on a network-on-chip for both best-effort and guaranteed service traffic. VLSI Design 2007 . Andreas Hansson, Kees Goossens, and Andrei R\u0103dulescu. 2007. A unified approach to mapping and routing on a network-on-chip for both best-effort and guaranteed service traffic. VLSI Design 2007."},{"key":"e_1_2_1_20_1","volume-title":"Proceedings of the 2004 Design, Automation and Test in Europe Conference and Exhibition.","volume":"1","author":"Hu Jingcao","year":"2004","unstructured":"Jingcao Hu and Radu Marculescu . 2004 . Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints . In Proceedings of the 2004 Design, Automation and Test in Europe Conference and Exhibition. Vol. 1 . IEEE, 234--239. Jingcao Hu and Radu Marculescu. 2004. Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints. In Proceedings of the 2004 Design, Automation and Test in Europe Conference and Exhibition. Vol. 1. IEEE, 234--239."},{"key":"e_1_2_1_22_1","unstructured":"IBM. 2012. CoreConnect Interconnect Standard. Retrieved from http:\/\/www-01.ibm.com\/chips\/techlib\/techlib.nsf\/products\/CoreConnect&lowbar;PLB6&lowbar;Peripheral_Cores. IBM. 2012. CoreConnect Interconnect Standard. Retrieved from http:\/\/www-01.ibm.com\/chips\/techlib\/techlib.nsf\/products\/CoreConnect&lowbar;PLB6&lowbar;Peripheral_Cores."},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.211"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2017079"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.898830"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.878260"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.828127"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2003.1206307"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/1255456.1255460"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF02289146"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/2001576.2001808"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2010691"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/1081081.1081128"},{"volume-title":"Synthesis and Optimization of Digital Circuits","author":"Micheli Giovanni De","key":"e_1_2_1_34_1","unstructured":"Giovanni De Micheli . 1994. Synthesis and Optimization of Digital Circuits . McGraw-Hill Higher Education , New York, NY . Giovanni De Micheli. 1994. Synthesis and Optimization of Digital Circuits. McGraw-Hill Higher Education, New York, NY."},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2004.03.003"},{"key":"e_1_2_1_36_1","volume-title":"Proceedings of the 14th Symposium on Computing: the Australasian Theory -","volume":"77","author":"Mujuni Egbert","year":"2008","unstructured":"Egbert Mujuni and Frances Rosamond . 2008 . Parameterized complexity of the clique partition problem . In Proceedings of the 14th Symposium on Computing: the Australasian Theory - Volume 77 (CATS\u201908). Australian Computer Society, Inc., Darlinghurst, Australia, 75--78. http:\/\/dl.acm.org\/citation.cfm&quest;id=1379361.1379375 Egbert Mujuni and Frances Rosamond. 2008. Parameterized complexity of the clique partition problem. In Proceedings of the 14th Symposium on Computing: the Australasian Theory - Volume 77 (CATS\u201908). Australian Computer Society, Inc., Darlinghurst, Australia, 75--78. http:\/\/dl.acm.org\/citation.cfm&quest;id=1379361.1379375"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.888284"},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.5555\/968879.969207"},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233573"},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/1084834.1084856"},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.91"},{"key":"e_1_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2005.1464952"},{"key":"e_1_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.134"},{"key":"e_1_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/1118299.1118309"},{"key":"e_1_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2012.6416720"},{"key":"e_1_2_1_46_1","unstructured":"STMicroelectronics. 2007. STBus Communication System: Concepts and Definitions. STMicroelectronics. STMicroelectronics. 2007. STBus Communication System: Concepts and Definitions. STMicroelectronics."},{"key":"e_1_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1162\/153244303321897735"},{"key":"e_1_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.5555\/2485288.2485709"},{"key":"e_1_2_1_49_1","unstructured":"Xilinx. 2012a. LogiCORE IP AXI Interconnect (v1.06.a). Xilinx. 2012a. LogiCORE IP AXI Interconnect (v1.06.a)."},{"key":"e_1_2_1_50_1","unstructured":"Xilinx. 2012b. Zynq-7000 All Programmable SoC Overview. Xilinx. 2012b. Zynq-7000 All Programmable SoC Overview."},{"key":"e_1_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2017442"}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2700075","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2700075","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T06:17:00Z","timestamp":1750227420000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2700075"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,4,30]]},"references-count":50,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2015,5,21]]}},"alternative-id":["10.1145\/2700075"],"URL":"https:\/\/doi.org\/10.1145\/2700075","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"type":"print","value":"1539-9087"},{"type":"electronic","value":"1558-3465"}],"subject":[],"published":{"date-parts":[[2015,4,30]]},"assertion":[{"value":"2013-11-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2014-09-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2015-04-30","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}