{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:16:48Z","timestamp":1750306608692,"version":"3.41.0"},"reference-count":36,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2015,4,21]],"date-time":"2015-04-21T00:00:00Z","timestamp":1429574400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"National Science Foundation","award":["CNS-0914474","CNS-1149285"],"award-info":[{"award-number":["CNS-0914474","CNS-1149285"]}]},{"name":"the I\/UCRC Program of the National Science Foundation","award":["EEC-0642422","IIP-1161022"],"award-info":[{"award-number":["EEC-0642422","IIP-1161022"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2015,5,21]]},"abstract":"<jats:p>Despite significant advantages, wider usage of field-programmable gate arrays (FPGAs) has been limited by lengthy compilation and a lack of portability. Virtual-architecture overlays have partially addressed these problems, but previous work focuses mainly on heavily pipelined applications with minimal control requirements. We expand previous work by enabling more flexible control via overlay architectures for finite-state machines. Although not appropriate for control-intensive circuits, the presented architectures reduced compilation times of control changes in a convolution case study from 7 hours to less than 1 second, with no performance overhead and an area overhead of 0.2%.<\/jats:p>","DOI":"10.1145\/2700082","type":"journal-article","created":{"date-parts":[[2015,4,22]],"date-time":"2015-04-22T13:57:35Z","timestamp":1429711055000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["Finite-State-Machine Overlay Architectures for Fast FPGA Compilation and Application Portability"],"prefix":"10.1145","volume":"14","author":[{"given":"Patrick","family":"Cooke","sequence":"first","affiliation":[{"name":"University of Florida, Gainesville, FL"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lu","family":"Hao","sequence":"additional","affiliation":[{"name":"University of Florida, Gainesville, FL"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Greg","family":"Stitt","sequence":"additional","affiliation":[{"name":"University of Florida, Gainesville, FL"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,4,21]]},"reference":[{"volume-title":"Retrieved","year":"2008","key":"e_1_2_1_1_1"},{"volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL\u201909)","year":"2009","author":"Asano S.","key":"e_1_2_1_2_1"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2007.43"},{"key":"e_1_2_1_4_1","first-page":"258","article-title":"State assignment for low power dissipation. Solid-State Circuits","volume":"30","author":"Benini L.","year":"1995","journal-title":"IEEE Journal of"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2012.25"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2008.24"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/234860.234862"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1878961.1878966"},{"key":"e_1_2_1_9_1","first-page":"108","article-title":"Fast and flexible high-level synthesis from OpenCL using reconfiguration contexts","volume":"2013","author":"Coole J.","year":"2013","journal-title":"IEEE Micro 99, PrePrints, 1. DOI:http:\/\/dx.doi.org\/10.1109\/MM."},{"key":"e_1_2_1_10_1","doi-asserted-by":"crossref","unstructured":"B. Cope P. Y. K. Cheung W. Luk and S. Witt. 2005. Have GPUs made FPGAs redundant in the field of video processing&quest; In Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology. 111--118. DOI:http:\/\/dx.doi.org\/10.1109\/FPT.2005.1568533  B. Cope P. Y. K. Cheung W. Luk and S. Witt. 2005. Have GPUs made FPGAs redundant in the field of video processing&quest; In Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology. 111--118. DOI:http:\/\/dx.doi.org\/10.1109\/FPT.2005.1568533","DOI":"10.1109\/FPT.2005.1568533"},{"volume-title":"Proceedings of the 35th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO\u201912)","author":"Culjak I.","key":"e_1_2_1_11_1"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1985.1270123"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145704"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2004.840301"},{"volume-title":"Proceedings of the IEEE International Symposium on Industrial Electronics (ISIE\u201907)","year":"2007","author":"Garcia-Vargas I.","key":"e_1_2_1_15_1"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/968280.968304"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2006.55"},{"key":"e_1_2_1_18_1","first-page":"23","article-title":"Finite state machine encoding for VHDL synthesis. Computers and Digital Techniques","volume":"148","author":"Kuusilinna K.","year":"2001","journal-title":"IEE Proceedings"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/2380403.2380427"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2009.5272463"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1046192.1046247"},{"volume-title":"Distributed as part of the MCNC International Workshop on Logic Synthesis","author":"McElvain K.","key":"e_1_2_1_22_1"},{"key":"e_1_2_1_23_1","doi-asserted-by":"crossref","unstructured":"S. McGettrick K. Patel and C. Bleakley. 2011. High performance programmable FPGA overlay for digital signal processing. In Reconfigurable Computing: Architectures Tools and Applications A. Koch R. Krishnamurthy J. McAllister R. Woods and T. El-Ghazawi (Eds.). Lecture Notes in Computer Science Vol. 6578. Springer Berlin 375--384. DOI:http:\/\/dx.doi.org\/10.1007\/978-3-642-19475-7_39   S. McGettrick K. Patel and C. Bleakley. 2011. High performance programmable FPGA overlay for digital signal processing. In Reconfigurable Computing: Architectures Tools and Applications A. Koch R. Krishnamurthy J. McAllister R. Woods and T. El-Ghazawi (Eds.). Lecture Notes in Computer Science Vol. 6578. Springer Berlin 375--384. DOI:http:\/\/dx.doi.org\/10.1007\/978-3-642-19475-7_39","DOI":"10.1007\/978-3-642-19475-7_39"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/277044.277235"},{"volume-title":"Retrieved","year":"2007","author":"Podlozhnyuk V.","key":"e_1_2_1_26_1"},{"volume-title":"Retrieved","year":"2000","author":"Pruteanu C.","key":"e_1_2_1_27_1"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2007.370382"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.766749"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1016\/S1383-7621(02)00067-X"},{"key":"e_1_2_1_31_1","unstructured":"V. Sklyarov and I. Skliarova. 2003. Architecture of a reconfigurable processor for implementing search algorithm over discrete matrices. In Engineering of Reconfigurable Systems and Algorithms. Citeseer 127--133.  V. Sklyarov and I. Skliarova. 2003. Architecture of a reconfigurable processor for implementing search algorithm over discrete matrices. In Engineering of Reconfigurable Systems and Algorithms. Citeseer 127--133."},{"volume-title":"Proceedings of the 2003 Euromicro Symposium on Digital System Design. 222--229","year":"2003","author":"Sklyarov V.","key":"e_1_2_1_32_1"},{"key":"e_1_2_1_33_1","unstructured":"T. Villa T. Kam R. K. Brayton and A. L. Sangiovanni-Vincentelli. 2012. Synthesis of Finite State Machines: Logic Optimization. Springer New York NY.   T. Villa T. Kam R. K. Brayton and A. L. Sangiovanni-Vincentelli. 2012. Synthesis of Finite State Machines: Logic Optimization. Springer New York NY."},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.59068"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2003.1275744"},{"volume-title":"Proceedings of the 4th Great Lakes Symposium on Design Automation of High Performance VLSI Systems. GLSV\u201994","year":"1994","author":"Yang W.-L.","key":"e_1_2_1_36_1"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.5555\/942792.943110"}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2700082","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2700082","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T06:17:00Z","timestamp":1750227420000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2700082"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,4,21]]},"references-count":36,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2015,5,21]]}},"alternative-id":["10.1145\/2700082"],"URL":"https:\/\/doi.org\/10.1145\/2700082","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"type":"print","value":"1539-9087"},{"type":"electronic","value":"1558-3465"}],"subject":[],"published":{"date-parts":[[2015,4,21]]},"assertion":[{"value":"2014-04-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2014-09-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2015-04-21","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}