{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:16:48Z","timestamp":1750306608585,"version":"3.41.0"},"reference-count":40,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2015,4,21]],"date-time":"2015-04-21T00:00:00Z","timestamp":1429574400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2015,5,21]]},"abstract":"<jats:p>\n            Cache memories in embedded systems play an important role in reducing the execution time of applications. Various kinds of extensions have been added to cache hardware to enable software involvement in replacement decisions, improving the runtime over a purely hardware-managed cache. Novel embedded systems, such as Intel\u2019s XScale and ARM Cortex processors, facilitate locking one or more lines in cache; this feature is called\n            <jats:italic>cache locking<\/jats:italic>\n            . We present a method in for instruction-cache locking that is able to reduce the average-case runtime of a program. We demonstrate that the optimal solution for instruction cache locking can be obtained in polynomial time. However, a fundamental lack of correlation between cache hardware and software program points renders such optimal solutions impractical.\n          <\/jats:p>\n          <jats:p>Instead, we propose two practical heuristics-based approaches to achieve cache locking. First, we present a static mechanism for locking the cache, in which the locked contents of the cache are kept fixed over the execution of the program. Next, we present a dynamic mechanism that accounts for changing program requirements at runtime. We devise a cost--benefit model to discover the memory addresses that should be locked in the cache. We implement our scheme inside a binary rewriter, widening the applicability of our scheme to binaries compiled using any compiler.<\/jats:p>\n          <jats:p>Results obtained on a suite of MiBench benchmarks show that our static mechanism results in 20% improvement in the instruction-cache miss rate on average and up to 18% improvement in the execution time on average for applications having instruction accesses as a bottleneck, compared to no cache locking. The dynamic mechanism improves the cache miss rate by 35% on average and execution time by 32% on instruction-cache-constrained applications.<\/jats:p>","DOI":"10.1145\/2700100","type":"journal-article","created":{"date-parts":[[2015,4,22]],"date-time":"2015-04-22T13:57:35Z","timestamp":1429711055000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":13,"title":["Instruction-Cache Locking for Improving Embedded Systems Performance"],"prefix":"10.1145","volume":"14","author":[{"given":"Kapil","family":"Anand","sequence":"first","affiliation":[{"name":"University of Maryland, College Park, Maryland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rajeev","family":"Barua","sequence":"additional","affiliation":[{"name":"University of Maryland, College Park, Maryland"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,4,21]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629395.1629422"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2465351.2465380"},{"key":"e_1_2_1_3_1","unstructured":"ARM Revised July 2007. ARM1156T2-S Technical Reference Manual. Retrieved from http:\/\/www.arm.com\/products\/CPUs\/families\/ARM11Family.html.  ARM Revised July 2007. ARM1156T2-S Technical Reference Manual. Retrieved from http:\/\/www.arm.com\/products\/CPUs\/families\/ARM11Family.html."},{"key":"e_1_2_1_4_1","unstructured":"ARM Revised March 2004. ARM Cortex A-8 Technical Reference Manual. Arm. Retreived from http:\/\/www.arm.com\/products\/CPUs\/families\/ARMCortexFamily. html.  ARM Revised March 2004. ARM Cortex A-8 Technical Reference Manual. Arm. Retreived from http:\/\/www.arm.com\/products\/CPUs\/families\/ARMCortexFamily. html."},{"volume-title":"Proceedings of the 14th International Conference on Real-Time and Network Systems (RNTS\u201906)","author":"Arnaud A.","key":"e_1_2_1_5_1","unstructured":"A. Arnaud and I. Puaut . 2006. Dynamic instruction cache locking in hard real-time systems . In Proceedings of the 14th International Conference on Real-Time and Network Systems (RNTS\u201906) . A. Arnaud and I. Puaut. 2006. Dynamic instruction cache locking in hard real-time systems. In Proceedings of the 14th International Conference on Real-Time and Network Systems (RNTS\u201906)."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/581888.581891"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/774789.774805"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1147\/sj.52.0078"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2004.09.004"},{"key":"e_1_2_1_10_1","unstructured":"BlackFin. 2009. ADSP-BF533 Processor Hardware Reference. Analog Devices. Retrieved from http:\/\/www. analog.com\/static\/imported-files\/processor_manuals\/bf533_hwr_Rev3.4.pdf.  BlackFin. 2009. ADSP-BF533 Processor Hardware Reference. Analog Devices. Retrieved from http:\/\/www. analog.com\/static\/imported-files\/processor_manuals\/bf533_hwr_Rev3.4.pdf."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2004.1255792"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1177\/109434200001400404"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/232973.232983"},{"volume-title":"Proceedings of the IASTED International Symposia Applied Informatics. 271--276","author":"Campoy A. Marti","key":"e_1_2_1_14_1","unstructured":"A. Marti Campoy , A. Perez Jimenez , A. Perles Ivars , and J. V. Busquets Mataix . 2001. Using genetic algorithms in content selection for locking-caches . In Proceedings of the IASTED International Symposia Applied Informatics. 271--276 . A. Marti Campoy, A. Perez Jimenez, A. Perles Ivars, and J. V. Busquets Mataix. 2001. Using genetic algorithms in content selection for locking-caches. In Proceedings of the IASTED International Symposia Applied Informatics. 271--276."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337523"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1086642.1086645"},{"key":"e_1_2_1_17_1","unstructured":"J. Edler and M. D. Hill. 2004. DineroIV Cache Simulator. Retrieved from http:\/\/www.cs.wisc.edu\/markhill\/DineroIV\/.  J. Edler and M. D. Hill. 2004. DineroIV Cache Simulator. Retrieved from http:\/\/www.cs.wisc.edu\/markhill\/DineroIV\/."},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1289816.1289853"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2002.4"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1057661.1057760"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/74926.74953"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.5555\/2190025.2190051"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837362"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTCSA.2009.59"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-011-0650-6"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/348019.348570"},{"key":"e_1_2_1_27_1","volume-title":"Proceedings of the 2nd International Workshop on Worst-Case Execution Time Analysis, in conjunction with the 14th Euromicro Conference on Real-Time Systems.","author":"Puaut I.","year":"2002","unstructured":"I. Puaut . 2002 . Cache analysis vs static cache locking for schedulability analysis in multitasking real-time systems . In Proceedings of the 2nd International Workshop on Worst-Case Execution Time Analysis, in conjunction with the 14th Euromicro Conference on Real-Time Systems. I. Puaut. 2002. Cache analysis vs static cache locking for schedulability analysis in multitasking real-time systems. In Proceedings of the 2nd International Workshop on Worst-Case Execution Time Analysis, in conjunction with the 14th Euromicro Conference on Real-Time Systems."},{"volume-title":"Proceedings of the 23rd IEEE International Real-Time Systems Symposium.","author":"Puaut I.","key":"e_1_2_1_28_1","unstructured":"I. Puaut and D. Decotigny . 2002. Low-complexity algorithms for static cache locking in multitasking hard real-time systems . In Proceedings of the 23rd IEEE International Real-Time Systems Symposium. I. Puaut and D. Decotigny. 2002. Low-complexity algorithms for static cache locking in multitasking hard real-time systems. In Proceedings of the 23rd IEEE International Real-Time Systems Symposium."},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/INTERACT.2005.7"},{"key":"e_1_2_1_30_1","unstructured":"Jan Sjodin Bo Froderberg and Thomas Lindgren. 1998. Allocation of global data objects in on-chip RAM. Compiler and Architecture Support for Embedded Computing Systems.  Jan Sjodin Bo Froderberg and Thomas Lindgren. 1998. Allocation of global data objects in on-chip RAM. Compiler and Architecture Support for Embedded Computing Systems."},{"volume-title":"Proceedings of the Conference on Design, Automation and Test in Europe. IEEE Computer Society, 409","author":"Steinke S.","key":"e_1_2_1_31_1","unstructured":"S. Steinke , L. Wehmeyer , B. Lee , and P. Marwedel . 2002. Assigning program and data objects to scratchpad for energy reduction . In Proceedings of the Conference on Design, Automation and Test in Europe. IEEE Computer Society, 409 . S. Steinke, L. Wehmeyer, B. Lee, and P. Marwedel. 2002. Assigning program and data objects to scratchpad for energy reduction. In Proceedings of the Conference on Design, Automation and Test in Europe. IEEE Computer Society, 409."},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.811113"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/291069.291050"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/1151074.1151085"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/781027.781062"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.5555\/968879.969148"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/1016720.1016748"},{"volume-title":"3rd Generation Intel XScale Microarchitecture Developer\u2019s Manual. Intel","key":"e_1_2_1_38_1","unstructured":"XScale. 2007. 3rd Generation Intel XScale Microarchitecture Developer\u2019s Manual. Intel . http:\/\/www.marvell.com\/application-processors\/pxa-family\/. XScale. 2007. 3rd Generation Intel XScale Microarchitecture Developer\u2019s Manual. Intel. http:\/\/www.marvell.com\/application-processors\/pxa-family\/."},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.5555\/1233791.1233796"},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/1113841.1113842"}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2700100","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2700100","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T06:17:00Z","timestamp":1750227420000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2700100"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,4,21]]},"references-count":40,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2015,5,21]]}},"alternative-id":["10.1145\/2700100"],"URL":"https:\/\/doi.org\/10.1145\/2700100","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"type":"print","value":"1539-9087"},{"type":"electronic","value":"1558-3465"}],"subject":[],"published":{"date-parts":[[2015,4,21]]},"assertion":[{"value":"2013-12-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2014-09-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2015-04-21","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}