{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:46:46Z","timestamp":1759146406039,"version":"3.41.0"},"reference-count":32,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2015,4,27]],"date-time":"2015-04-27T00:00:00Z","timestamp":1430092800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2015,4,27]]},"abstract":"<jats:p>\n            The\n            <jats:italic>network-on-chip<\/jats:italic>\n            (NoC) technology allows for integration of a manycore design on a single chip for higher efficiency and scalability.\n            <jats:italic>Three-dimensional<\/jats:italic>\n            (3D) NoCs offer several advantages over\n            <jats:italic>two-dimensional<\/jats:italic>\n            (2D) NoCs.\n            <jats:italic>Through-silicon via<\/jats:italic>\n            (TSV) technology is one of the candidates for implementation of 3D NoCs. TSV reliability analysis is still challenging for 3D NoC designers because of their unique electrical, thermal, and physical characteristics. After providing an overview of common TSV issues, this article aims to define a reliability criterion for NoC and provide a framework for quantifying this reliability as it relates to TSV issues. TSV issues are modeled as a time-invariant failure probability. Also, a reliability criterion for TSV-based NoC is defined. The relationship between NoC reliability and TSV failure is quantified. For the first time, the reliability criterion is reduced to a tractable closed-form expression that requires a single Monte Carlo simulation. Importantly, the Monte Carlo simulation depends only on network geometry. To demonstrate our proposed method, the reliability criterion of a simple 8\u00d78\u00d78 NoC supported by an 8\u00d78\u00d77 network of TSVs is calculated.\n          <\/jats:p>","DOI":"10.1145\/2700236","type":"journal-article","created":{"date-parts":[[2015,4,28]],"date-time":"2015-04-28T12:43:57Z","timestamp":1430225037000},"page":"1-16","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["Analytical Reliability Analysis of 3D NoC under TSV Failure"],"prefix":"10.1145","volume":"11","author":[{"given":"Misagh","family":"Khayambashi","sequence":"first","affiliation":[{"name":"University of California, Irvine, CA"}]},{"given":"Pooria M.","family":"Yaghini","sequence":"additional","affiliation":[{"name":"University of California, Irvine, CA"}]},{"given":"Ashkan","family":"Eghbal","sequence":"additional","affiliation":[{"name":"University of California, Irvine, CA"}]},{"given":"Nader","family":"Bagherzadeh","sequence":"additional","affiliation":[{"name":"University of California, Irvine, CA"}]}],"member":"320","published-online":{"date-parts":[[2015,4,27]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2005.1554447"},{"volume-title":"Proceedings of the 1st International Workshop on Networks-on-Chip Architectures (NoCArc'08)","author":"Bahn J. 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Lee . 2006. 3D on-chip networking technology based on post-silicon devices for future networks-on-chip . In Proceedings of the 1st International Conference on Nano-Networks and Workshops (NanoNet'06) . 1--5. S. Fujita, K. Nomura, K. Abe, and T. H. Lee. 2006. 3D on-chip networking technology based on post-silicon devices for future networks-on-chip. In Proceedings of the 1st International Conference on Nano-Networks and Workshops (NanoNet'06). 1--5."},{"key":"e_1_2_1_11_1","unstructured":"ITRS. 2012. Executive summary. http:\/\/www.itrs.net\/Links\/2012ITRS\/Home2012.html.  ITRS. 2012. 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Failure mechanisms and optimum design for electroplated copper through-silicon vias (TSV). In Proceedings of the 59th Electronic Components and Technology Conference (ECTC'09). 624--629."},{"volume-title":"Proceedings of the 59th Electronic Components and Technology Conference (ECTC'09)","author":"Lu K. H.","key":"e_1_2_1_17_1","unstructured":"K. H. Lu , X. Zhang , S.-K. Ryu , J. Im , R. Huang , and P. S. Ho . 2009. Thermo-mechanical reliability of 3-D ICs containing through silicon vias . In Proceedings of the 59th Electronic Components and Technology Conference (ECTC'09) . 630--634. K. H. Lu, X. Zhang, S.-K. Ryu, J. Im, R. Huang, and P. S. Ho. 2009. Thermo-mechanical reliability of 3-D ICs containing through silicon vias. In Proceedings of the 59th Electronic Components and Technology Conference (ECTC'09). 630--634."},{"key":"e_1_2_1_18_1","volume-title":"Nanoscale Transistors: Device Physics, Modeling and Simulation","author":"Lundstrom M.","year":"2006","unstructured":"M. Lundstrom and J. Guo . 2006 . Nanoscale Transistors: Device Physics, Modeling and Simulation . Springer . http:\/\/books.google.com\/books&quest;id&equals;dXeecjkvFQC. M. Lundstrom and J. Guo. 2006. Nanoscale Transistors: Device Physics, Modeling and Simulation. Springer. http:\/\/books.google.com\/books&quest;id&equals;dXeecjkvFQC."},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429450"},{"key":"e_1_2_1_20_1","doi-asserted-by":"crossref","unstructured":"A. Mercha G. Van der Plas V. Moroz I. De Wolf P. Asimakopoulos N. Minas S. Domae D. Perry M. Choi A. Redolfi C. Okoro Y. Yang J. Van Olmen S. Thangaraju D. Sabuncuoglu Tezcan P. Soussan J. H. Cho A. Yakovlev P. Marchal Y. Travaly E. Beyne S. Biesemans and B. Swinnen. 2010. Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k\/metal gate CMOS performance. In Proceedings of the IEEE International Electron Devices Meeting (IEDM'10). 2.2.1--2.2.4.  A. Mercha G. Van der Plas V. Moroz I. De Wolf P. Asimakopoulos N. Minas S. Domae D. Perry M. Choi A. Redolfi C. Okoro Y. Yang J. Van Olmen S. Thangaraju D. Sabuncuoglu Tezcan P. Soussan J. H. Cho A. Yakovlev P. Marchal Y. Travaly E. Beyne S. Biesemans and B. Swinnen. 2010. Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k\/metal gate CMOS performance. In Proceedings of the IEEE International Electron Devices Meeting (IEDM'10). 2.2.1--2.2.4.","DOI":"10.1109\/IEDM.2010.5703278"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2010.5560225"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.893649"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cds.2011.0349"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1088\/0960-1317\/18\/7\/075018"},{"key":"e_1_2_1_25_1","unstructured":"P. H. Roth C. Jacobi and K. Weber. 2012. Superprocessors and supercomputers. In Chips 2020 Bernd Hoefflinger Ed. Springer 421--427.  P. H. Roth C. Jacobi and K. Weber. 2012. Superprocessors and supercomputers. In Chips 2020 Bernd Hoefflinger Ed. Springer 421--427."},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2012.2194784"},{"volume-title":"Proceedings of the 58th Electronic Components and Technology Conference (ECTC'08)","author":"Selvanayagam C. S.","key":"e_1_2_1_27_1","unstructured":"C. S. Selvanayagam , J. H. Lau , X. Zhang , S. K. W. Seah , K. Vaidyanathan , and T. C. Chai . 2008. Nonlinear thermal stress\/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps . In Proceedings of the 58th Electronic Components and Technology Conference (ECTC'08) . 1073--1081. C. S. Selvanayagam, J. H. Lau, X. Zhang, S. K. W. Seah, K. Vaidyanathan, and T. C. Chai. 2008. Nonlinear thermal stress\/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps. In Proceedings of the 58th Electronic Components and Technology Conference (ECTC'08). 1073--1081."},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2010.09.031"},{"key":"e_1_2_1_29_1","volume-title":"A. Opdebeeck, M. Rakowski, B. de Wachter, M. Dehan, M. Nelis, R. Agarwal, W. Dehaene, Y. Travaly, P. Marchal, and E. Beyne.","author":"Van der Plas G.","year":"2010","unstructured":"G. Van der Plas , P. Limaye , A. Mercha , H. Oprins , C. Torregiani , S. Thijs , D. Linten , M. Stucchi , K. Guruprasad , D. Velenis , D. Shinichi , V. Cherman , B. Vandevelde , V. Simons , I. de Wolf , R. Labie , D. Perry , S. Bronckers , N. Minas , M. Cupac , W. Ruythooren , J. Van Olmen , A. Phommahaxay , M. de Potter de Ten Broeck , A. Opdebeeck, M. Rakowski, B. de Wachter, M. Dehan, M. Nelis, R. Agarwal, W. Dehaene, Y. Travaly, P. Marchal, and E. Beyne. 2010 . Design issues and considerations for low-cost 3D TSV IC technology. In IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC '10). 148--149. G. Van der Plas, P. Limaye, A. Mercha, H. Oprins, C. Torregiani, S. Thijs, D. Linten, M. Stucchi, K. Guruprasad, D. Velenis, D. Shinichi, V. Cherman, B. Vandevelde, V. Simons, I. de Wolf, R. Labie, D. Perry, S. Bronckers, N. Minas, M. Cupac, W. Ruythooren, J. Van Olmen, A. Phommahaxay, M. de Potter de Ten Broeck, A. Opdebeeck, M. Rakowski, B. de Wachter, M. Dehan, M. Nelis, R. Agarwal, W. Dehaene, Y. Travaly, P. Marchal, and E. Beyne. 2010. Design issues and considerations for low-cost 3D TSV IC technology. In IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC'10). 148--149."},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1002\/mop.26021"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/PDP.2010.21"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2011.106"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2700236","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2700236","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T05:07:43Z","timestamp":1750223263000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2700236"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,4,27]]},"references-count":32,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2015,4,27]]}},"alternative-id":["10.1145\/2700236"],"URL":"https:\/\/doi.org\/10.1145\/2700236","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"type":"print","value":"1550-4832"},{"type":"electronic","value":"1550-4840"}],"subject":[],"published":{"date-parts":[[2015,4,27]]},"assertion":[{"value":"2014-03-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2014-09-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2015-04-27","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}